公开(公告)号：US11386036B2

公开(公告)日：2022-07-12

申请号：US16404461

申请日：2019-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Saurabh Goyal ,  Bhupendra Sharma ,  Huanzhang Huang ,  Douglas Edward Wente ,  Suzanne Mary Vining ,  Mustafa Ulvi Erdogan

IPC: G06F13/42 ,  G06F13/38 ,  H04L12/46 ,  H03F3/45 ,  H04B3/58

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.

公开(公告)号：US10922255B2

公开(公告)日：2021-02-16

申请号：US16939725

申请日：2020-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Douglas Edward Wente ,  Mustafa Ulvi Erdogan ,  Huanzhang Huang ,  Saurabh Goyal ,  Bhupendra Sharma

IPC: G06F13/42 ,  G06F13/38 ,  H04B3/36

Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

公开(公告)号：US10298238B2

公开(公告)日：2019-05-21

申请号：US15600378

申请日：2017-05-19

Applicant: Texas Instruments Incorporated

Inventor： Weicheng Zhang ,  Huanzhang Huang ,  Yanli Fan ,  Roland Sperlich

IPC: H03K17/16 ,  H03K19/0944 ,  H03K19/0185

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

公开(公告)号：US09130792B2

公开(公告)日：2015-09-08

申请号：US14299187

申请日：2014-06-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Roland Sperlich ,  Huanzhang Huang ,  Charles M. Branch

IPC: H03K5/159 ,  H04L25/02 ,  H04B3/14

CPC classification number: H04L27/01 ,  H04B3/144 ,  H04L25/026 ,  H04L25/03019 ,  H04L25/03885

Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。

公开(公告)号：US11580053B2

公开(公告)日：2023-02-14

申请号：US17347920

申请日：2021-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Suzanne Mary Vining ,  Yonghui Tang ,  Douglas Edward Wente ,  Huanzhang Huang

IPC: G06F13/42

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

公开(公告)号：US10972081B2

公开(公告)日：2021-04-06

申请号：US16804061

申请日：2020-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yanfei Jiang ,  Huanzhang Huang ,  Yonghui Tang ,  Shita Guo

IPC: H03K5/00 ,  H03K5/1252 ,  H03K19/20 ,  H03K19/0175 ,  G05F1/46

Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.

公开(公告)号：US10938385B2

公开(公告)日：2021-03-02

申请号：US16936462

申请日：2020-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang Huang ,  Amit Rane

IPC: G06F13/38 ,  H03K17/00 ,  H03K19/003 ,  H03K17/56

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

公开(公告)号：US10536138B1

公开(公告)日：2020-01-14

申请号：US16130814

申请日：2018-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang Huang ,  Jikai Chen ,  Yanli Fan ,  Md Anwar Sadat

IPC: H03K5/15 ,  H03K5/24

Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.

公开(公告)号：US20170257098A1

公开(公告)日：2017-09-07

申请号：US15600378

申请日：2017-05-19

Applicant: Texas Instruments Incorporated

Inventor： Weicheng Zhang ,  Huanzhang Huang ,  Yanli Fan ,  Roland Sperlich

IPC: H03K19/0944

CPC classification number: H03K19/0944 ,  H03K19/018578

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

公开(公告)号：US11068435B2

公开(公告)日：2021-07-20

申请号：US16751411

申请日：2020-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Suzanne Mary Vining ,  Yonghui Tang ,  Douglas Edward Wente ,  Huanzhang Huang

IPC: G06F13/42

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.