公开(公告)号：US20170169742A1

公开(公告)日：2017-06-15

申请号：US15441498

申请日：2017-02-24

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Mamoru ISHIZAKI ,  Isao Ebisawa

IPC: G09F9/35 ,  G09F3/20 ,  G09G3/34 ,  A47F5/00 ,  G09G3/36

CPC classification number: G09F9/35 ,  A47F5/00 ,  A47F5/0018 ,  G09F3/204 ,  G09F3/208 ,  G09F9/301 ,  G09G3/344 ,  G09G3/3648 ,  G09G2300/026 ,  G09G2380/02 ,  G09G2380/04

Abstract: A display panel for a shelf board including a display part which displays the information and is to be placed on a front surface of a shelf board, a driving part which drives the display part and is to be placed on an underside of the shelf board along the shelf board, and a wiring part connecting the display part and the driving part. The wiring part extends from an outer periphery of the display part and is bent from a lower edge portion or an upper edge portion of the front surface toward the underside of the shelf board.

公开(公告)号：US20160013213A1

公开(公告)日：2016-01-14

申请号：US14861059

申请日：2015-09-22

Applicant: Toppan Printing Co., Ltd.

Inventor： Mamoru ISHIZAKI

IPC: H01L27/12 ,  H01L29/08

CPC classification number: H01L27/1222 ,  H01L27/124 ,  H01L29/0847 ,  H01L29/41733

Abstract: A thin film transistor array including a gate wiring connected to a gate electrode and extended in a first direction, a source wiring connected to a source electrode, a drain electrode having a gap from the source electrode, a semiconductor pattern formed at least in a portion corresponding to the gap between the source and drain electrodes, the semiconductor pattern having a region defined by extending the portion in a second direction perpendicular to the first direction, and a pixel electrode that overlaps with a capacitor electrode in the planar view. In the planar view, the drain electrode has a shape of a single line, the source electrode has a first portion in a line shape and a second portion in a sheath shape surrounding the drain electrode and keeping a space from the drain electrode, and the source wiring is narrower than the region of the semiconductor pattern.

Abstract translation: 一种薄膜晶体管阵列，包括连接到栅电极并沿第一方向延伸的栅极布线，连接到源电极的源极布线，与源电极具有间隙的漏极电极，至少部分地形成的半导体图案 对应于源电极和漏电极之间的间隙，半导体图案具有通过在与第一方向垂直的第二方向上延伸该部分而限定的区域，以及在平面图中与电容器电极重叠的像素电极。 在平面图中，漏电极具有单线形状，源电极具有线状的第一部分和围绕漏极的护套形状的第二部分，并且与漏电极保持空间， 源极布线比半导体图案的区域窄。