公开(公告)号：US20190331979A1

公开(公告)日：2019-10-31

申请号：US16504019

申请日：2019-07-05

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Takehisa TAKADA ,  Mamoru ISHIZAKI

IPC: G02F1/167 ,  G09G3/34 ,  G02F1/16761 ,  G02F1/16766

Abstract: A display device including a pair of substrates having surfaces facing each other and electrodes formed on the surfaces, respectively, a display medium having a memory effect and formed between the pair of substrates, and a drive unit that applies a drive voltage to the display medium. The display medium includes charged particles encapsulated therein such that movement of the charged particles based on a voltage applied by the drive unit provides display, and the charged particles include first particles for displaying a first color with application of a first voltage, second particles for displaying a second color with application of a second voltage having a polarity different from a polarity of the first voltage, and third particles for displaying a third color with application of a third voltage which has the same polarity as the polarity of the first voltage and an absolute value smaller than an absolute value of the first voltage.

公开(公告)号：US20150221685A1

公开(公告)日：2015-08-06

申请号：US14664683

申请日：2015-03-20

Applicant: Toppan Printing Co., Ltd.

Inventor： Mamoru ISHIZAKI ,  Kaoru Hatta

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/1292 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/66825 ,  H01L29/788 ,  H01L2224/11

Abstract: A layered structure includes a first electrode layer on an insulating substrate, a first insulating film on the first electrode layer, a second electrode layer on the first insulating film, a second insulating film on the second electrode layer, and a third electrode layer on the second insulating film. The first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected. The third electrode layer relays or reinforces, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer formed on the first insulating film.

Abstract translation: 分层结构包括绝缘基板上的第一电极层，第一电极层上的第一绝缘膜，第一绝缘膜上的第二电极层，第二电极层上的第二绝缘膜和第二绝缘膜上的第三电极层 第二绝缘膜。 第一电极层，第一绝缘膜的开口，第二电极层，第二绝缘膜的开口和第三电极层具有使第一电极层和第二电极层连接的堆叠结构。 第三电极层通过第二绝缘膜的开口继续或加强第一电极层和形成在第一绝缘膜上的第二电极层之间的连接。

公开(公告)号：US20180203270A1

公开(公告)日：2018-07-19

申请号：US15921797

申请日：2018-03-15

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Mamoru ISHIZAKI

IPC: G02F1/1345 ,  G02F1/1368 ,  G02F1/1362 ,  G09F9/30

CPC classification number: G02F1/1345 ,  G02F1/136213 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  G09F9/00 ,  G09F9/30 ,  G09G3/36 ,  G09G2300/0408 ,  G09G2300/0426

Abstract: A thin-film transistor array including an insulating substrate, gate lines formed on the insulating substrate, source lines formed on the insulating substrate, and transistors each being formed on the insulating substrate at a position corresponding to a respective intersection of the gate lines and the source lines, and formed in a matrix including pixels in rows and columns, each of the transistors including a gate electrode connected to each of the gate lines, a source electrode connected to each of the source lines, a drain electrode, and a pixel electrode connected to the drain electrode. Each of the source lines is connected to a column of pixels, and each of the gate lines includes a first portion connected to a predetermined number of pixels in a row and a second portion connected to pixels in an adjacent row.

公开(公告)号：US20160211280A1

公开(公告)日：2016-07-21

申请号：US14980314

申请日：2015-12-28

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Mamoru ISHIZAKI

IPC: H01L27/12 ,  G09G3/36 ,  G09G3/34

CPC classification number: H01L27/1244 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/136259 ,  G02F2001/136263 ,  G02F2001/136272 ,  G02F2201/50 ,  G09G3/344 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2320/0204 ,  G09G2320/0233 ,  G09G2330/08 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259

Abstract: A thin-film transistor array includes thin-film transistors each including an insulating substrate which is formed with a gate electrode, a gate wiring, a capacitor electrode and a capacitor wiring. A source electrode and a drain electrode having a gap therebetween and including a semiconductor pattern are formed, in a region overlapping with the gate electrode on the substrate via a gate insulator, with the semiconductor pattern being covered with a protective layer. Two such TFTs are independently formed for each pixel. In each pixel, two source electrodes are separately connected to two respective source wirings, and two drain electrodes are connected to an electrode of the pixel via individual drain-connecting electrodes. The array includes source-connecting electrodes each connecting between the source electrodes of the two TFTs formed for each pixel. The same drive waveform is applied to the two source wirings.

Abstract translation: 薄膜晶体管阵列包括薄膜晶体管，每个薄膜晶体管包括形成有栅电极，栅极布线，电容器电极和电容器布线的绝缘基板。 在栅极绝缘体与衬底上的栅电极重叠的区域中形成具有间隙的源电极和漏电极，并且半导体图案被保护层覆盖。 对于每个像素独立地形成两个这样的TFT。 在每个像素中，两个源电极分别连接到两个相应的源极布线，并且两个漏电极通过单独的漏极连接电极连接到像素的电极。 该阵列包括各自连接在为每个像素形成的两个TFT的源电极之间的源极连接电极。 相同的驱动波形被应用到两个源极布线。

公开(公告)号：US20210183903A1

公开(公告)日：2021-06-17

申请号：US17188306

申请日：2021-03-01

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Mamoru ISHIZAKI ,  Katsuhiko MOROSAWA

IPC: H01L27/12

Abstract: A thin film transistor array includes column wirings extending in a first direction, row wirings extending in a second direction, capacitor wirings, and pixels formed in a matrix. Each pixel includes a thin film transistor, a pixel electrode, and a capacitor electrode. The pixels form a rectangular effective region of an M column by N row matrix structure in which N pixels are formed in the first direction and M pixels are formed in the second direction, where M and N are natural numbers, the row wirings each have a length extending across the M pixels formed in the second direction in the effective region, the column wirings each have a length extending across the N/2 pixels formed in the first direction in the effective region, and the capacitor wirings each have a length which extends across the N pixels formed in the first direction in the effective region.

公开(公告)号：US20190271878A1

公开(公告)日：2019-09-05

申请号：US16415559

申请日：2019-05-17

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Tomoko TSURUDA ,  Mamoru ISHIZAKI

IPC: G02F1/1335 ,  G02F1/157 ,  G02F1/1677 ,  G02F1/167

Abstract: A reflective display apparatus including a reflective display portion which is two-dimensionally divided into pixels each having subpixels and changes reflectance of each subpixel based on an image signal, and colored layers facing the reflective display portion and partially overlapping the pixels as viewed in a facing direction in which the colored layers face the reflective display portion. The colored layers include traversing colored layers that overlap more than one of the subpixels as viewed in the facing direction, and the colored layers are positioned such that at most one of the colored layers overlaps one of the subpixels as viewed in the facing direction.

公开(公告)号：US20210263356A1

公开(公告)日：2021-08-26

申请号：US17318194

申请日：2021-05-12

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Mamoru ISHIZAKI

IPC: G02F1/1368 ,  G02F1/1362

Abstract: A thin-film transistor array includes an insulating substrate and pixels each including a thin-film transistor, a pixel electrode, and a capacitor electrode, the pixels being formed in a matrix and located at positions where column wirings extending in a column direction intersect row wirings perpendicular to the column wirings and extending in a row direction. The thin-film transistor includes a gate electrode, a source electrode, a drain electrode, and a semiconductor pattern formed between the source electrode and the drain electrode. The pixel electrode includes two electrically conductive layers which are a lower layer electrode serving as a lower pixel electrode, and an upper layer electrode serving as an upper pixel electrode. The corresponding one of the column wirings is at a position which has no overlap with the capacitor electrode and the lower pixel electrode, and has an overlap with the upper pixel electrode, in the lamination direction.

公开(公告)号：US20210183902A1

公开(公告)日：2021-06-17

申请号：US17188205

申请日：2021-03-01

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Mamoru ISHIZAKI

IPC: H01L27/12 ,  H01L29/417

Abstract: A thin film transistor array includes column wirings and row wirings formed on an insulating substrate and extending perpendicularly to each other, and pixels formed at crossing points of the column and row wirings. Each of the pixels includes a pixel electrode and a thin film transistor that includes a gate electrode, a source electrode, a drain electrode, and a semiconductor pattern. The source electrode has a linear shape having a constant width in a plan view, the drain electrode includes a U-shaped portion positioned around the source electrode such that a gap is formed between the U-shaped portion and the source electrode in the plan view, the semiconductor pattern connects at least the source electrode and the drain electrode such that a channel region is formed, and the gate electrode overlaps the channel region via a gate insulating film and includes the channel region in the plan view.

公开(公告)号：US20180024391A1

公开(公告)日：2018-01-25

申请号：US15706831

申请日：2017-09-18

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Mamoru ISHIZAKI

IPC: G02F1/1343 ,  H01L29/786 ,  H01L21/822 ,  G02F1/1362

CPC classification number: G02F1/1343 ,  G02F1/1362 ,  G02F1/136204 ,  G03F7/00 ,  G09F9/30 ,  G09F9/35 ,  H01L21/822 ,  H01L27/04 ,  H01L27/1255 ,  H01L27/1292 ,  H01L29/786

Abstract: A thin-film transistor array including an insulating substrate, a gate insulating film sandwiched between a first structure and a second structure, the first structure including a gate electrode, a gate wire connected to the gate electrode, a capacitor electrode, and a capacitor wire connected to the capacitor electrode, and the second structure including a source electrode, a source wire connected to the source electrode, a drain electrode, and a pixel electrode connected to the drain electrode, a resistor inserted between parts of the capacitor wire, and a semiconductor layer formed between the source electrode and the drain electrode. The pixel electrode is positioned over the capacitor electrode with the gate insulating film positioned therebetween and has a storage capacitance, and the source electrode and the drain electrode are positioned over the gate electrode with the gate insulating film positioned therebetween.

公开(公告)号：US20170221968A1

公开(公告)日：2017-08-03

申请号：US15487529

申请日：2017-04-14

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Ryohei MATSUBARA ,  Mamoru ISHIZAKI ,  Makoto NISHIZAWA

IPC: H01L27/28 ,  H01L51/05 ,  H01L51/10 ,  H01L51/00

CPC classification number: H01L27/283 ,  G02F1/1368 ,  H01L27/285 ,  H01L29/786 ,  H01L51/0004 ,  H01L51/0558 ,  H01L51/107

Abstract: A thin-film transistor array includes a substrate and thin-film transistors positioned in matrix on the substrate. The thin-film transistors each include source and drain electrodes formed on a gate insulation layer, and a semiconductor layer formed on the gate insulation layer and positioned between the source and drain electrodes. The semiconductor layer is formed in stripes over the plurality of thin-film transistors such that one of the stripes has a long axis direction coinciding with a channel width direction of one of the thin-film transistors. The semiconductor layer has a cross section in a short axis direction of the stripe such that a thickness of the semiconductor layer gradually decreases outwardly from a center portion of the stripe.