公开(公告)号：US10998443B2

公开(公告)日：2021-05-04

申请号：US15130205

申请日：2016-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Huan-Tsung Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.

公开(公告)号：US20190131299A1

公开(公告)日：2019-05-02

申请号：US16227578

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Chia-Hsin Hu ,  Jaw-Juinn Horng

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  G05F1/56

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.