公开(公告)号：US09378314B2

公开(公告)日：2016-06-28

申请号：US14467327

申请日：2014-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Jaw-Juinn Horng ,  Yung-Chow Peng ,  Shih-Cheng Yang ,  Chung-Kai Lin

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5036 ,  G06F17/5072 ,  G06F2217/10 ,  G06F2217/78 ,  H01L27/0207

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.

Abstract translation: 一种用于设计集成电路并预测金属氧化物半导体（MOS）阵列中的电流失配的系统和方法。 选择MOS阵列中的单元的第一子集，并且对这些单元中的每一个进行电流测量。 相对于参考单元的电流确定单元的第一子集中的每个单元的电流的标准偏差。 可以使用确定的第一子集中的一个或多个单元的电流的标准偏差来确定局部变化的标准偏差。 然后可以确定由阵列的x和/或y方向由例如多晶密度梯度效应引起的变化的标准偏差，并且由阵列确定阵列中的任何单元的电流失配。

公开(公告)号：US08832619B2

公开(公告)日：2014-09-09

申请号：US13751195

申请日：2013-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Jaw-Juinn Horng ,  Yung-Chow Peng ,  Shih-Cheng Yang ,  Chung-Kai Lin

IPC: G06F17/50 ,  G06F9/455 ,  G06F17/10

CPC classification number: G06F17/5036 ,  G06F17/5072 ,  G06F2217/10 ,  G06F2217/78 ,  H01L27/0207

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.

Abstract translation: 一种用于设计集成电路并预测金属氧化物半导体（MOS）阵列中的电流失配的系统和方法。 选择MOS阵列中的单元的第一子集，并且对这些单元中的每一个进行电流测量。 相对于参考单元的电流确定单元的第一子集中的每个单元的电流的标准偏差。 可以使用确定的第一子集中的一个或多个单元的电流的标准偏差来确定局部变化的标准偏差。 然后可以确定由阵列的x和/或y方向由例如多晶密度梯度效应引起的变化的标准偏差，并且由阵列确定阵列中的任何单元的电流失配。

公开(公告)号：US20190131299A1

公开(公告)日：2019-05-02

申请号：US16227578

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Chia-Hsin Hu ,  Jaw-Juinn Horng

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  G05F1/56

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

公开(公告)号：US11244944B2

公开(公告)日：2022-02-08

申请号：US16227578

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Chia-Hsin Hu ,  Jaw-Juinn Horng

IPC: H01L27/08 ,  H01L27/088 ,  H01L21/8234 ,  G05F1/56 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

公开(公告)号：US10163899B2

公开(公告)日：2018-12-25

申请号：US15365469

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Chia-Hsin Hu ,  Jaw-Juinn Horng

IPC: G05F1/56 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.