公开(公告)号：US11621351B2

公开(公告)日：2023-04-04

申请号：US17306536

申请日：2021-05-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Huan-Tsung Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.

公开(公告)号：US09812444B2

公开(公告)日：2017-11-07

申请号：US15592256

申请日：2017-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsin Hu ,  Hsueh-Shih Fan ,  Huan-Tsung Huang

IPC: H01L29/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L23/535 ,  H01L21/768 ,  H01L29/161

CPC classification number: H01L27/0629 ,  H01L21/2053 ,  H01L21/76895 ,  H01L21/823431 ,  H01L23/535 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66166 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.

公开(公告)号：US12033937B2

公开(公告)日：2024-07-09

申请号：US17099002

申请日：2020-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02 ,  H10B43/27

CPC classification number: H01L23/5228 ,  H01L28/00 ,  H01L28/24 ,  H10B43/27

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US20180151562A1

公开(公告)日：2018-05-31

申请号：US15365469

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit KUNDU ,  Chia-Hsin Hu ,  Jaw-Juinn Horng

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  G05F1/56

CPC classification number: H01L27/0886 ,  G05F1/56 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/785

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

公开(公告)号：US09773731B2

公开(公告)日：2017-09-26

申请号：US15009500

申请日：2016-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/24

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US10170414B2

公开(公告)日：2019-01-01

申请号：US15693083

申请日：2017-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11582

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US09166067B2

公开(公告)日：2015-10-20

申请号：US14089808

申请日：2013-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jaw-Juinn Horng ,  Chung-Hui Chen ,  Sun-Jay Chang ,  Chia-Hsin Hu

IPC: H01L27/02 ,  H01L29/861 ,  H01L27/08

CPC classification number: H01L29/8611 ,  H01L27/0207 ,  H01L27/0814 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.

Abstract translation: 带隙参考电路包括耦合在第一电源节点和一对中间电压节点之间的基于误差放大器的电流镜，以及用于提供比例绝对温度（PTAT）电流的匹配二极管对。 匹配二极管对包括连接在来自一对中间电压节点的第一中间电压节点和第二电源节点之间的第一二极管，以及与来自所述一对中间电压的第二中间电压节点之间的电阻器串联连接的第二二极管 节点和第二个供应节点。 每个二极管具有一个同相结合的P-N二极管结。

公开(公告)号：US11244944B2

公开(公告)日：2022-02-08

申请号：US16227578

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Chia-Hsin Hu ,  Jaw-Juinn Horng

IPC: H01L27/08 ,  H01L27/088 ,  H01L21/8234 ,  G05F1/56 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

公开(公告)号：US10163899B2

公开(公告)日：2018-12-25

申请号：US15365469

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Chia-Hsin Hu ,  Jaw-Juinn Horng

IPC: G05F1/56 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

公开(公告)号：US09691758B1

公开(公告)日：2017-06-27

申请号：US15068068

申请日：2016-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsin Hu ,  Hsueh-Shih Fan ,  Huan-Tsung Huang

IPC: H01L21/8234 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/16 ,  H01L29/24 ,  H01L29/267 ,  H01L21/205

CPC classification number: H01L27/0629 ,  H01L21/2053 ,  H01L21/76895 ,  H01L21/823431 ,  H01L23/535 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66166 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.