公开(公告)号：US12087575B2

公开(公告)日：2024-09-10

申请号：US17577726

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L21/8234

CPC classification number: H01L21/02274 ,  H01L21/28518 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/823864 ,  H01L23/53266 ,  H01L21/823418

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.