公开(公告)号：US20220139707A1

公开(公告)日：2022-05-05

申请号：US17577726

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US10804097B2

公开(公告)日：2020-10-13

申请号：US16568720

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/8234

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US11742404B2

公开(公告)日：2023-08-29

申请号：US17169892

申请日：2021-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun Chieh Wang ,  Yueh-Ching Pai

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/49 ,  H01L21/28 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8234

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, conductive layers are formed on the gate dielectric layer to fully fill the gate space, the gate dielectric layer and the conducive layers are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not includes tungsten, and the contact metal layer includes tungsten.

公开(公告)号：US20210013033A1

公开(公告)日：2021-01-14

申请号：US17036734

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US11232945B2

公开(公告)日：2022-01-25

申请号：US17036734

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/762 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/8234

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US20210257263A1

公开(公告)日：2021-08-19

申请号：US17232381

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun Chieh Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L29/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

公开(公告)号：US10971602B2

公开(公告)日：2021-04-06

申请号：US16852819

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Shun Liao ,  Huai-Tei Yang ,  Chun Chieh Wang ,  Yueh-Ching Pai ,  Chun-I Wu

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66

Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.

公开(公告)号：US20240363442A1

公开(公告)日：2024-10-31

申请号：US18770052

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun Chieh Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823857 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/823418 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

公开(公告)号：US20240363339A1

公开(公告)日：2024-10-31

申请号：US18771110

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/532

CPC classification number: H01L21/02274 ,  H01L21/28518 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/823864 ,  H01L23/53266 ,  H01L21/823418

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US12107015B2

公开(公告)日：2024-10-01

申请号：US17232381

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun Chieh Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823857 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/823418 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.