公开(公告)号：US12125791B2

公开(公告)日：2024-10-22

申请号：US17209657

申请日：2021-03-23

申请人： Samsung Electronics Co., Ltd.

发明人： Jeeyong Kim ,  Junghwan Lee

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC分类号： H01L23/535 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

摘要： A semiconductor device includes: a substrate including a memory cell region and a connection region; a plurality of gate lines vertically overlapping each other in the memory cell region of the substrate in a vertical direction, each gate line including a first metal; a stepped connection unit in the connection region and comprising a plurality of conductive pad regions, each conductive pad region including the first metal and integrally connected to a respective gate line of the plurality of gate lines; a plurality of contact structures vertically overlapping the stepped connection unit, each contact structure connected to a respectively corresponding conductive pad region of the plurality of conductive pad regions and including a second metal; and at least one metal silicide layer between at least one contact structure and the respectively corresponding conductive pad region.

公开(公告)号：US11854874B2

公开(公告)日：2023-12-26

申请号：US17086754

申请日：2020-11-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L21/76858 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2221/1073 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

公开(公告)号：US11791405B2

公开(公告)日：2023-10-17

申请号：US17375598

申请日：2021-07-14

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Alexei Sadovnikov ,  Natalia Lavrovskaya

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L21/768 ,  H01L29/45 ,  H01L21/02 ,  H01L29/49 ,  H01L21/311 ,  H01L29/08 ,  H01L21/324

CPC分类号： H01L29/7393 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/31105 ,  H01L21/324 ,  H01L21/76889 ,  H01L29/0808 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66325

摘要： An integrated circuit includes a transistor that has an collector region, a base region laterally surrounded by the collector region, and an emitter region laterally surrounded by the base region. A silicide layer on the emitter region is laterally spaced apart from the base region by an unsilicided ring. The emitter region is laterally spaced apart from a base contact region that may be covered by a dielectric layer such as a gate oxide layer.

公开(公告)号：US11749603B2

公开(公告)日：2023-09-05

申请号：US17811649

申请日：2022-07-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/3065 ,  H01L23/528

CPC分类号： H01L23/53209 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/485 ,  H01L23/528 ,  H01L23/535 ,  H01L23/53266 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/7848

摘要： A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

公开(公告)号：US20230170397A1

公开(公告)日：2023-06-01

申请号：US18103306

申请日：2023-01-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Ming HSU ,  Pei-Yu CHOU ,  Chih-Pin TSAO ,  Kuang-Yuan HSU ,  Jyh-Huei CHEN

IPC分类号： H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/45 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823418 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886 ,  H01L29/665 ,  H01L29/41791 ,  H01L29/66795 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76855

摘要： A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

公开(公告)号：US20190074284A1

公开(公告)日：2019-03-07

申请号：US16176634

申请日：2018-10-31

申请人： TOSHIBA MEMORY CORPORATION

发明人： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC分类号： H01L27/11556 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/1157 ,  H01L21/74 ,  H01L21/768 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11578

CPC分类号： H01L27/11556 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of theNAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20190035677A1

公开(公告)日：2019-01-31

申请号：US16070172

申请日：2016-03-30

申请人： Intel Corporation

发明人： Manish CHANDHOK ,  Richard E. SCHENKER ,  Hui Jae YOO ,  Kevin L. LIN ,  Jasmeet S. CHAWLA ,  Stephanie A. BOJARSKI ,  Satyarth SURI ,  Colin T. CARVER ,  Sudipto NASKAR

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC分类号： H01L21/76802 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53271

摘要： A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

公开(公告)号：US20180362568A1

公开(公告)日：2018-12-20

申请号：US16061049

申请日：2016-12-12

申请人： TOSOH CORPORATION ,  SAGAMI CHEMICAL RESEARCH INSTITUTE

发明人： Naoyuki KOISO ,  Yuki YAMAMOTO ,  Hiroyuki OIKE ,  Teppei HAYAKAWA ,  Taishi FURUKAWA ,  Ken-ichi TADA

IPC分类号： C07F17/02 ,  H01L29/49 ,  H01L29/45 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  C23C16/18

CPC分类号： C07F17/02 ,  C07F15/06 ,  C07F17/00 ,  C07F19/00 ,  C23C16/18 ,  H01L21/02175 ,  H01L21/02271 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76889 ,  H01L23/53238 ,  H01L29/456 ,  H01L29/4975

摘要： Provided is a cobalt complex which is useful for the production of a cobalt-containing thin film under conditions where no oxidizing gas is used. A cobalt complex represented by general formula (1) (wherein R1 represents a silyloxy group represented by general formula (2) (wherein R6, R7 and R8 independently represent an alkyl group having 1 to 6 carbon atoms); R2 represents a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, or a silyloxy group represented by general formula (2); R3, R4 and R5 independently represent a hydrogen atom or an alkyl group having 1 to 6 carbon atoms; and L represents a diene having 4 to 10 carbon atoms) is used.

公开(公告)号：US20180342455A1

公开(公告)日：2018-11-29

申请号：US15605204

申请日：2017-05-25

申请人： SANDISK TECHNOLOGIES LLC

发明人： Yosuke NOSHO ,  Han-Min KIM

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L23/528 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/53295 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor structure includes a semiconductor device located over a substrate, a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer, and at least one second dielectric material layer overlying the semiconductor device, and interconnect structures including metallic lines and metallic vias and embedded within the dielectric layer stack. The interconnect structures also include a metal silicide portion that directly contacts the silicon nitride layer. A combination of the silicon nitride layer and the metal silicide portion provides a continuous hydrogen barrier structure that is vertically spaced from the top surface of the semiconductor device.

公开(公告)号：US20180277427A1

公开(公告)日：2018-09-27

申请号：US15988145

申请日：2018-05-24

申请人： GLOBALFOUNDRIES INC.

发明人： Viraj SARDESAI ,  Suraj K. PATIL ,  Scott BEASOR ,  Vimal Kumar KAMINENI

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/76849 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/5226 ,  H01L23/53209

摘要： A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.