公开(公告)号：US09570561B2

公开(公告)日：2017-02-14

申请号：US14179601

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Yi-Ju Chen ,  Sheng-Fu Yu ,  I-Shan Huang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/36 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/26586 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7854 ,  H01L2029/7858

Abstract: Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

Abstract translation: 一些实施例涉及包括一个或多个finFET器件的集成电路（IC）。 finFET包括从半导体衬底向上延伸的半导体材料的鳍。 具有第一掺杂类型的第一和第二源极/漏极区域在翅片中彼此间隔开。 沟道区域设置在翅片中并且将第一和第二源极/漏极区彼此物理分离。 沟道区具有与第一掺杂类型相反的第二掺杂型。 导电栅极电极跨过沟道区域的鳍状物并且通过栅极电介质与沟道区域分离。 具有第一掺杂类型的浅掺杂区域设置在翅片周围的上侧壁和侧壁翅片区域附近。 浅掺杂区域在栅电极的外边缘之间的栅电极下连续延伸。

公开(公告)号：US20240243190A1

公开(公告)日：2024-07-18

申请号：US18622230

申请日：2024-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

公开(公告)号：US20220216317A1

公开(公告)日：2022-07-07

申请号：US17700172

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pohan Kung ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

公开(公告)号：US20210257481A1

公开(公告)日：2021-08-19

申请号：US16943687

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.