公开(公告)号：US12021130B2

公开(公告)日：2024-06-25

申请号：US18171128

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ying Hsin Lu ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ling-Sung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L29/786

CPC classification number: H01L29/42376 ,  H01L27/088 ,  H01L29/404 ,  H01L29/42392 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

公开(公告)号：US11502185B2

公开(公告)日：2022-11-15

申请号：US16882014

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  Ling-Sung Wang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

公开(公告)号：US11949000B2

公开(公告)日：2024-04-02

申请号：US17874286

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L31/062 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L31/113

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

公开(公告)号：US20220367688A1

公开(公告)日：2022-11-17

申请号：US17874286

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

公开(公告)号：US11588038B2

公开(公告)日：2023-02-21

申请号：US17175368

申请日：2021-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ying Hsin Lu ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ling-Sung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L29/786

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

公开(公告)号：US11476351B2

公开(公告)日：2022-10-18

申请号：US16943687

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L31/062 ,  H01L31/113 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

公开(公告)号：US20240243190A1

公开(公告)日：2024-07-18

申请号：US18622230

申请日：2024-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

公开(公告)号：US20230207650A1

公开(公告)日：2023-06-29

申请号：US18171128

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ying Hsin Lu ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ling-Sung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L27/088 ,  H01L29/404 ,  H01L29/42392 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

公开(公告)号：US20210305386A1

公开(公告)日：2021-09-30

申请号：US17175368

申请日：2021-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ying Hsin Lu ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ling-Sung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L29/786

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

公开(公告)号：US20210257481A1

公开(公告)日：2021-08-19

申请号：US16943687

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.