公开(公告)号：US10665673B2

公开(公告)日：2020-05-26

申请号：US16263656

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L21/02 ,  H01L29/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell; forming first fin active regions in the well tape cell and second fin active regions in the IC cell; forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tape cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tape cell.

公开(公告)号：US10529824B2

公开(公告)日：2020-01-07

申请号：US16049545

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-De Chiou ,  Hui-Chi Chen ,  Jeng-Ya Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.