公开(公告)号：US10651289B2

公开(公告)日：2020-05-12

申请号：US16195102

申请日：2018-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-De Chiou ,  Janet Chen ,  Jeng-Ya Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

公开(公告)号：US20200286993A1

公开(公告)日：2020-09-10

申请号：US16881467

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

公开(公告)号：US12027415B2

公开(公告)日：2024-07-02

申请号：US17815177

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya Yeh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41775 ,  H01L21/31111 ,  H01L21/31116 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US11476156B2

公开(公告)日：2022-10-18

申请号：US17001189

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya Yeh

IPC: H01L29/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/311

Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US11387321B2

公开(公告)日：2022-07-12

申请号：US16881467

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L21/02 ,  H01L29/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

公开(公告)号：US20200006484A1

公开(公告)日：2020-01-02

申请号：US16263656

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/762 ,  H01L29/417

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell; forming first fin active regions in the well tape cell and second fin active regions in the IC cell; forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tape cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tape cell.

公开(公告)号：US11908896B2

公开(公告)日：2024-02-20

申请号：US17859731

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L29/0847 ,  H01L21/02381 ,  H01L21/02579 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/41791

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

公开(公告)号：US20220352318A1

公开(公告)日：2022-11-03

申请号：US17859731

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

公开(公告)号：US11443984B2

公开(公告)日：2022-09-13

申请号：US16983018

申请日：2020-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Chi Chen ,  Hsiang-Ku Shen ,  Jeng-Ya Yeh

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a n-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

公开(公告)号：US11107810B2

公开(公告)日：2021-08-31

申请号：US16561362

申请日：2019-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Pin Tsao ,  Jeng-Ya Yeh ,  Chia-Wei Soong

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/11 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/535

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and the substrate includes a first region and a second region. A gate structure is formed over a fin structure and a first S/D structure has a first volume. A second S/D structure has a second volume, and the second volume is lower than the first volume. A first contact structure is formed over the first S/D structure and a first conductive via is formed over the first contact structure. A power line is formed over the first conductive via, and the power line is electrically connected to the first S/D structure by the first conductive via and the first contact structure.