公开(公告)号：US20210249952A1

公开(公告)日：2021-08-12

申请号：US16991335

申请日：2020-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alan Roth ,  Haohua Zhou ,  Eric Soenen ,  Ying-Chih Hsu ,  Paul Ranucci ,  Mei Hsu Wong ,  Tze-Chiang Huang

IPC: H02M3/156 ,  H01L23/498 ,  H01L23/495 ,  H01L23/58

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

公开(公告)号：US10719648B2

公开(公告)日：2020-07-21

申请号：US15260143

申请日：2016-09-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tze-Chiang Huang ,  Kai-Yuan Ting ,  Sandeep Kumar Goel ,  Yun-Han Lee ,  Shereef Shehata ,  Mei Wong

IPC: G06F17/50 ,  G06F30/367 ,  G06F30/33 ,  G06Q50/18 ,  G06F115/08 ,  G06F119/06

Abstract: A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.

公开(公告)号：US20220058144A1

公开(公告)日：2022-02-24

申请号：US16999055

申请日：2020-08-20

Applicant: Global Unichip Corporation ,  Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Igor Elkanovich ,  Amnon Parnass ,  Pei Yu ,  Li-Ken Yeh ,  Yung-Sheng Fang ,  Sheng-Wei Lin ,  Tze-Chiang Huang ,  King Ho Tam ,  Ching-Fang Chen

IPC: G06F13/16 ,  H01L25/065 ,  H01L23/00

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

公开(公告)号：US20220037288A1

公开(公告)日：2022-02-03

申请号：US17135312

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Haohua Zhou ,  Mei Hsu Wong ,  Tze-Chiang Huang

IPC: H01L25/065 ,  H01L23/525 ,  H03K5/24 ,  H03K19/20

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.

公开(公告)号：US12136609B2

公开(公告)日：2024-11-05

申请号：US18344282

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Haohua Zhou ,  Mei Hsu Wong ,  Tze-Chiang Huang

IPC: H01L25/065 ,  H01L23/525 ,  H03K5/24 ,  H03K19/20

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.

公开(公告)号：US10599796B2

公开(公告)日：2020-03-24

申请号：US15724671

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Charlie Zhou ,  Tze-Chiang Huang ,  Jack Liu

IPC: G06F17/50 ,  G06F7/58

Abstract: A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.

公开(公告)号：US09830413B2

公开(公告)日：2017-11-28

申请号：US15201328

申请日：2016-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sandeep Kumar Goel ,  Tze-Chiang Huang ,  Yun-Han Lee

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5022 ,  G06F2217/66 ,  G06F2217/78

Abstract: A method is disclosed that includes establishing an intellectual property (IP) bank, an application bank, and a technology bank; selecting valid configurations from the IP bank for corresponding IPs and at least one subsystem based on the application data, for generating in response to a user-defined requirement, by a model generator, a performance, power, area and cost (PPAC) model of the valid configurations; based on the PPAC model, creating at least one architecture comprising at least one of the corresponding IPs, and at least one of the valid configurations for the at least one of the corresponding IPs; and, estimating, by a PPAC explorer assessing the technology bank, at least one of a performance value, a power value, an area value and a cost value for a fabrication of the at least one architecture by simulating available fabrication process technology based on the technology bank.