公开(公告)号：US20230223304A1

公开(公告)日：2023-07-13

申请号：US17662940

申请日：2022-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L21/823418 ,  H01L21/31116 ,  H01L29/42392 ,  H01L21/823437 ,  H01L21/823468

Abstract: A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.