公开(公告)号：US20210257156A1

公开(公告)日：2021-08-19

申请号：US17169118

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ka Fai CHANG ,  Chin-Chou LIU ,  Fong-Yuan CHANG ,  Hui Yu LEE ,  Yi-Kan CHENG

IPC: H01F27/34 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

公开(公告)号：US20210173998A1

公开(公告)日：2021-06-10

申请号：US17179904

申请日：2021-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Cheng-Hung YEH ,  Po-Hsiang HUANG ,  Sen-Bor JAN ,  Yi-Kan CHENG ,  Hsiu-Chuan SHU

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

公开(公告)号：US20200328202A1

公开(公告)日：2020-10-15

申请号：US16912061

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung CHEN ,  Jerry Chang-Jui KAO ,  Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Shao-Huan WANG ,  XinYong WANG ,  Yi-Kan CHENG ,  Chun-Chen CHEN

IPC: H01L27/02 ,  G06F30/394 ,  G06F30/398

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

公开(公告)号：US20230205967A1

公开(公告)日：2023-06-29

申请号：US18171072

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Cheng-Hung YEH ,  Po-Hsiang HUANG ,  Sen-Bor JAN ,  Yi-Kan CHENG ,  Hsiu-Chuan SHU

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

公开(公告)号：US20130254726A1

公开(公告)日：2013-09-26

申请号：US13902102

申请日：2013-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chang HSU ,  Ying-Yu SHEN ,  Wen-Ju YANG ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/70

Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

Abstract translation: 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。