公开(公告)号：US20230253396A1

公开(公告)日：2023-08-10

申请号：US18300142

申请日：2023-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Chun-Chen CHEN ,  Sheng-Hsiung CHEN ,  Ting-Wei CHIANG ,  Chung-Te LIN ,  Jung-Chan YANG ,  Lee-Chung LU ,  Po-Hsiang HUANG

IPC: H01L27/02 ,  H01L27/118 ,  G06F30/394 ,  G06F30/392

CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/394 ,  H01L27/11807 ,  H01L2027/11875

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US20200328202A1

公开(公告)日：2020-10-15

申请号：US16912061

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung CHEN ,  Jerry Chang-Jui KAO ,  Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Shao-Huan WANG ,  XinYong WANG ,  Yi-Kan CHENG ,  Chun-Chen CHEN

IPC: H01L27/02 ,  G06F30/394 ,  G06F30/398

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

公开(公告)号：US20220067266A1

公开(公告)日：2022-03-03

申请号：US17523600

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung CHEN ,  Jerry Chang-Jui KAO ,  Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Shao-Huan WANG ,  XinYong WANG ,  Yi-Kan CHENG ,  Chun-Chen CHEN

IPC: G06F30/398 ,  H01L27/02 ,  G06F30/394

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

公开(公告)号：US20190103392A1

公开(公告)日：2019-04-04

申请号：US15966507

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Sheng-Hsiung CHEN ,  Ting-Wei CHIANG ,  Chung-Te LIN ,  Jung-Chan YANG ,  Lee-Chung LU ,  Po-Hsiang HUANG ,  Chun-Chen CHEN

IPC: H01L27/02 ,  H01L27/118 ,  G06F17/50

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a wire cut between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the wire cut separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US20210004517A1

公开(公告)日：2021-01-07

申请号：US17029985

申请日：2020-09-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Huan WANG ,  Sheng-Hsiung CHEN ,  Wen-Hao CHEN ,  Chun-Chen CHEN ,  Hung-Chih OU

IPC: G06F30/394 ,  G06F30/20 ,  G06F30/327 ,  G06F30/392 ,  G06F30/3312

Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.

公开(公告)号：US20190266309A1

公开(公告)日：2019-08-29

申请号：US16410761

申请日：2019-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Huan WANG ,  Sheng-Hsiung CHEN ,  Wen-Hao CHEN ,  Chun-Chen CHEN ,  Hung-Chih OU

IPC: G06F17/50

Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.

公开(公告)号：US20180165403A1

公开(公告)日：2018-06-14

申请号：US15616907

申请日：2017-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Huan WANG ,  Sheng-Hsiung CHEN ,  Wen-Hao CHEN ,  Chun-Chen CHEN ,  Hung-Chih OU

IPC: G06F17/50 ,  H01L23/522 ,  H01L23/528

CPC classification number: G06F17/5077 ,  G06F17/5009 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5072 ,  G06F2217/06 ,  G06F2217/84 ,  H01L23/5226

Abstract: A system is includes a processor and a computer readable medium. The computer readable medium connected to the processor. The computer readable medium is configured to store instructions. The processor is configured to execute the instructions for determining, according to at least one parameter of a cell in a semiconductor device indicated by a design file, a layout pattern indicating a via pillar structure that meets an electromigration (EM) rule. The via pillar structure comprises metal layers and at least one via, and the at least one via is coupled to the metal layers. The processor is further configured to execute the instructions for including, in the design file, the layout pattern indicating the via pillar structure. The processor is further configured to execute the instructions for generating data which indicate the design file, for fabrication of the semiconductor device.

公开(公告)号：US20210265336A1

公开(公告)日：2021-08-26

申请号：US17315900

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Lee-Chung LU ,  Po-Hsiang HUANG ,  Chun-Chen CHEN ,  Chung-Te LIN ,  Ting-Wei CHIANG ,  Sheng-Hsiung CHEN ,  Jung-Chan YANG

IPC: H01L27/02 ,  H01L27/118 ,  G06F30/394 ,  G06F30/392

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US20200152617A1

公开(公告)日：2020-05-14

申请号：US16744975

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan CHANG ,  Sheng-Hsiung CHEN ,  Ting-Wei CHIANG ,  Chung-Te LIN ,  Jung-Chan YANG ,  Lee-Chung LU ,  Po-Hsiang HUANG ,  Chun-Chen CHEN

IPC: H01L27/02 ,  G06F30/394 ,  H01L27/118

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US20170352623A1

公开(公告)日：2017-12-07

申请号：US15171862

申请日：2016-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan CHANG ,  Sheng-Hsiung CHEN ,  Po-Hsiang HUANG ,  Jyun-Hao CHANG ,  Chun-Chen CHEN

IPC: H01L23/528 ,  G06F17/50 ,  H01L23/522

CPC classification number: H01L23/5283 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: An integrated circuit includes at least one first conductive feature and at least one second conductive feature. The second conductive feature has at least one extension portion, and the extension portion of the second conductive feature is protruded from the projection of the first conductive feature on the second conductive feature. The integrated circuit further includes at least one third conductive feature, and at least one first conductive via electrically connecting the third conductive feature and the extension portion of the second conductive feature.