公开(公告)号：US11244866B2

公开(公告)日：2022-02-08

申请号：US16932268

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Lain-Jong Li ,  Tzu-Chiang Chen

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L29/06 ,  H01L21/02 ,  B82Y40/00

Abstract: In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.

公开(公告)号：US20210376133A1

公开(公告)日：2021-12-02

申请号：US16887729

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.