公开(公告)号：US11710700B2

公开(公告)日：2023-07-25

申请号：US17391216

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53276 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US20210398898A1

公开(公告)日：2021-12-23

申请号：US16908942

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

公开(公告)号：US20210082832A1

公开(公告)日：2021-03-18

申请号：US16573817

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Min-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US10141260B1

公开(公告)日：2018-11-27

申请号：US15605987

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76879 ,  H01L23/53266 ,  H01L23/53295

Abstract: A method of forming an interconnection structure includes forming a dielectric structure over a non-insulator structure; forming a hole in the dielectric structure to expose the non-insulator structure; forming a first diffusion barrier layer into the hole in the dielectric structure using a first deposition process; forming a second diffusion barrier layer over the first diffusion barrier layer using a second deposition process that is different from the first deposition process; and forming a metal over the second diffusion barrier layer.