公开(公告)号：US20150115328A1

公开(公告)日：2015-04-30

申请号：US14587747

申请日：2014-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Po-Chih CHEN ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chun-Wei HSU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/778 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer.

Abstract translation: 半导体结构包括第一层。 第一层包括第一III-V族半导体材料。 半导体结构还包括在第一层上的第二层。 第二层包括与第一III-V族半导体材料不同的第二III-V族半导体材料。 半导体结构还包括在第二层上的绝缘层。 图案化绝缘层以暴露第一层的一部分。 第一层的暴露部分包括第二层的电子。 半导体结构还包括在第一层的暴露部分上的金属间化合物。

公开(公告)号：US20230253455A1

公开(公告)日：2023-08-10

申请号：US18301461

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Yu-Syuan LIN ,  Jiun-Lei YU ,  Ming-Cheng LIN ,  Chun Lin TSAI

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/06 ,  H01L29/47 ,  H02M3/158

CPC classification number: H01L29/1075 ,  H01L29/7787 ,  H01L29/0649 ,  H01L29/475 ,  H01L29/0661 ,  H01L29/7786 ,  H02M3/1588 ,  H01L29/2003

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

公开(公告)号：US20210280689A1

公开(公告)日：2021-09-09

申请号：US17303331

申请日：2021-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chen-Ju YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/43 ,  H01L29/778 ,  H01L29/10 ,  H01L29/267 ,  H01L21/02

Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US20190131442A1

公开(公告)日：2019-05-02

申请号：US16219281

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Yu-Syuan LIN ,  Jiun-Lei YU ,  Ming-Cheng LIN ,  Chun Lin TSAI

IPC: H01L29/778 ,  H02M3/00 ,  H01L29/47 ,  H01L29/10 ,  H01L29/06 ,  H02M3/158

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

公开(公告)号：US20180350945A1

公开(公告)日：2018-12-06

申请号：US16101065

申请日：2018-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chen-Ju YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/10 ,  H01L29/778 ,  H01L29/43 ,  H01L29/417 ,  H01L29/267

CPC classification number: H01L29/66462 ,  H01L21/02271 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/432 ,  H01L29/7786 ,  H01L2924/0002

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US20170358671A1

公开(公告)日：2017-12-14

申请号：US15664767

申请日：2017-07-31

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Yu-Syuan LIN ,  Jiun-Lei YU ,  Ming-Cheng LIN ,  Chun Lin TSAI

IPC: H01L29/778 ,  H01L29/47 ,  H02M3/00 ,  H01L29/10 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/7786 ,  H02M3/00 ,  H02M3/1588 ,  Y02B70/1466

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

公开(公告)号：US20170317184A1

公开(公告)日：2017-11-02

申请号：US15645463

申请日：2017-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chen-Ju YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L21/02 ,  H01L29/267 ,  H01L29/20 ,  H01L29/417 ,  H01L29/43

CPC classification number: H01L29/66462 ,  H01L21/02271 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/432 ,  H01L29/7786 ,  H01L2924/0002

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US20160293694A1

公开(公告)日：2016-10-06

申请号：US15185735

申请日：2016-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Yi SU ,  Fu-Chih YANG ,  Chun Lin TSAI ,  Chih-Chang CHENG ,  Ruey-Hsin LIU

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L49/02 ,  H01L29/861 ,  H01L29/36 ,  H01L23/535

Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

Abstract translation: 这里描述了高压半导体器件。 示例性的半导体器件包括设置在衬底中的第一掺杂区域和第二掺杂区域。 第一掺杂区域和第二掺杂区域相对地掺杂并相邻地设置在衬底中。 第一隔离结构和第二隔离结构设置在衬底上，使得每个隔离结构至少部分地设置在第一掺杂区域上。 第一隔离结构与第二隔离结构间隔开。 电阻器设置在第一隔离结构的一部分上并电耦合到第一掺杂区域。 设置在第二掺杂区域的一部分上并且电耦合到第二掺杂区域的场板。

公开(公告)号：US20140187002A1

公开(公告)日：2014-07-03

申请号：US14200777

申请日：2014-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Po-Chih CHEN ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chun-Wei HSU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66

CPC classification number: H01L29/7784 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A method of forming a semiconductor structure having a substrate is disclosed. The semiconductor structure includes a first layer formed in contact with the substrate. The first layer made of a first III-V semiconductor material selected from GaN, GaAs and InP. A second layer is formed on the first layer. The second layer made of a second III-V semiconductor material selected from AlGaN, AlGaAs and AlInP. An interface is between the first layer and the second layer forms a carrier channel. An insulating layer is formed on the second layer. Portions of the insulating layer and the second layer are removed to expose a top surface of the first layer. A metal feature is formed in contact with the carrier channel and the metal feature is annealed to form a corresponding intermetallic compound.

Abstract translation: 公开了一种形成具有基板的半导体结构的方法。 半导体结构包括与衬底接触形成的第一层。 第一层由选自GaN，GaAs和InP的第一III-V族半导体材料制成。 在第一层上形成第二层。 第二层由选自AlGaN，AlGaAs和AlInP的第二III-V半导体材料制成。 在第一层和第二层之间的界面形成载体通道。 绝缘层形成在第二层上。 除去绝缘层和第二层的部分以露出第一层的顶表面。 形成与载体通道接触的金属特征，金属特征退火以形成对应的金属间化合物。