公开(公告)号：US20180277646A1

公开(公告)日：2018-09-27

申请号：US15990241

申请日：2018-05-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Wei YAO ,  Chen-Ju YU ,  King-Yuen WONG ,  Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/205 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/452 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/28575 ,  H01L29/0843 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

公开(公告)号：US20200373408A1

公开(公告)日：2020-11-26

申请号：US16947616

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chen-Ju YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/43 ,  H01L29/778 ,  H01L29/267

Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US20190252510A1

公开(公告)日：2019-08-15

申请号：US16394368

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Wei YAO ,  Chen-Ju YU ,  King-Yuen WONG ,  Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/45 ,  H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02 ,  H01L29/205 ,  H01L29/417

CPC classification number: H01L29/452 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/28575 ,  H01L29/0843 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second compound layer between the salicide source feature and the salicide drain feature.

公开(公告)号：US20150295055A1

公开(公告)日：2015-10-15

申请号：US14751999

申请日：2015-06-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Liang CHU ,  Fei-Yuh CHEN ,  Yi-Sheng CHEN ,  Shih-Kuang HSIAO ,  Chun Lin TSAI ,  Kong-Beng THEI

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/78 ,  H01L29/7823 ,  H01L29/7835

Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.

Abstract translation: 晶体管包括围绕有源区的隔离区。 晶体管还包括位于有源区域的一部分上的栅极电介质层。 晶体管还包括在栅极电介质层上的栅电极。 栅极电介质层下方的有源区的部分包括漏极区和源极区之间的沟道区，以及与沟道区邻接的至少一个翼区。 所述至少一个机翼区域具有邻接所述通道区域的基部边缘。 至少一个翼区域是多边形或弯曲的。

公开(公告)号：US20200303496A1

公开(公告)日：2020-09-24

申请号：US16899706

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Yi SU ,  Fu-Chih YANG ,  Chun Lin TSAI ,  Chih-Chang CHENG ,  Ruey-Hsin LIU

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/861 ,  H01L49/02 ,  H01L27/08 ,  H01L23/535 ,  H01L29/36 ,  H01L29/66

Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

公开(公告)号：US20150072496A1

公开(公告)日：2015-03-12

申请号：US14533822

申请日：2014-11-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ker Hsiao HUO ,  Chih-Chang CHENG ,  Ru-Yi SU ,  Jen-Hao YEH ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/265 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7393

Abstract: A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region.

Abstract translation: 制造高电压半导体晶体管的方法包括在具有第一导电类型的衬底上生长第一阱区域，第一阱区域具有第二类型的导电性。 首先，具有第一类型导电性的第二阱区的第二和第三部分被掺杂到第一阱区中。 第一绝缘层生长在第二阱区内的第一阱部分中和之上。 在第二阱区的第三部分上的衬底上生长第二绝缘层。 反冲穿区被掺杂到第一阱区中。 栅极结构形成在衬底上。 在栅极结构的与第一绝缘层相反的一侧的第二阱区的第一部分中形成源极区。 在第一阱区中形成漏极区。

公开(公告)号：US20140197488A1

公开(公告)日：2014-07-17

申请号：US14212081

申请日：2014-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Chang CHENG ,  Ruey-Hsin LIU ,  Chih-Wen YAO ,  Chia-Chin SHEN ,  Eric HUANG ,  Fu Chin YANG ,  Chun Lin TSAI ,  Chin Tuan HSIAO

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L24/16 ,  H01L24/48 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type.

Abstract translation: 形成器件的方法包括在衬底中形成第一掺杂剂类型的掩埋阱区域。 第一掺杂剂类型的阱区形成在掩埋阱区上。 在第一掺杂剂类型的阱区和第一掺杂剂类型的掩埋阱区之间形成第二掺杂剂类型的第一阱区。 第二掺杂剂类型的第二阱区形成在第一掺杂剂类型的阱区中。 至少部分地在第一掺杂剂类型的阱区域中形成隔离结构。 第一栅电极形成在隔离结构和第二掺杂剂类型的第二阱区上。

公开(公告)号：US20140035035A1

公开(公告)日：2014-02-06

申请号：US14051655

申请日：2013-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ker Hsiao HUO ,  Chih-Chang CHENG ,  Ru-Yi SU ,  Jen-Hao YEH ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7394 ,  H01L21/26533 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66325 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Abstract translation: 在本公开中提供了高电压金属氧化物半导体横向扩散器件（HV LDMOS），特别是绝缘栅双极结型晶体管（IGBT）及其制造方法。 该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱 好。 栅极，源极，第二掺杂阱，第一阱的一部分和漏极结构的一部分被硅衬底中的深沟槽隔离特征和注入的氧层包围。

公开(公告)号：US20160308023A1

公开(公告)日：2016-10-20

申请号：US15192889

申请日：2016-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chen-Ju YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L29/43 ,  H01L29/778 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/66462 ,  H01L21/02271 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/432 ,  H01L29/7786 ,  H01L2924/0002

Abstract: A method of forming a high electron mobility transistor (HEMT) that includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are formed on the second III-V compound layer. A p-type layer is deposited on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is formed on a portion of the p-type layer.

Abstract translation: 一种形成包括在第一III-V化合物层上外延生长第二III-V化合物层的高电子迁移率晶体管（HEMT）的方法。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 源特征和漏极特征形成在第二III-V复合层上。 在源特征和漏极特征之间的第二III-V化合物层的一部分上沉积p型层。 栅电极形成在p型层的一部分上。

公开(公告)号：US20150349087A1

公开(公告)日：2015-12-03

申请号：US14825866

申请日：2015-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fu-Wei YAO ,  Chen-Ju YU ,  King-Yuen WONG ,  Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/452 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/28575 ,  H01L29/0843 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A method of forming a high electron mobility transistor (HEMT) includes epitaxially growing a second III-V compound layer on a first III-V compound layer. The method further includes partially etching the second III-V compound layer to form two through holes in the second III-V compound layer. Additionally, the method includes forming a silicon feature in each of two through holes. Furthermore, the method includes depositing a metal layer on each silicon feature. Moreover, the method includes annealing the metal layer and each silicon feature to form corresponding salicide source/drain features. The method also includes forming a gate electrode over the second III-V compound layer between the salicide source/drain features.

Abstract translation: 形成高电子迁移率晶体管（HEMT）的方法包括在第一III-V化合物层上外延生长第二III-V化合物层。 该方法还包括部分蚀刻第二III-V化合物层以在第二III-V化合物层中形成两个通孔。 此外，该方法包括在两个通孔中的每一个中形成硅特征。 此外，该方法包括在每个硅特征上沉积金属层。 此外，该方法包括对金属层和每个硅特征退火以形成相应的自对准硅源/漏极特征。 该方法还包括在硅化物源极/漏极特征之间的第二III-V化合物层上形成栅电极。