公开(公告)号：US07181717B1

公开(公告)日：2007-02-20

申请号：US10868625

申请日：2004-06-15

申请人： Deshanand P. Singh ,  Stephen D. Brown ,  Terry P. Borer ,  Chris Sanford ,  Gabriel Quan

发明人： Deshanand P. Singh ,  Stephen D. Brown ,  Terry P. Borer ,  Chris Sanford ,  Gabriel Quan

IPC分类号： H03K17/693 ,  G06F17/50 ,  G01R31/28

CPC分类号： G06F17/5031 ,  G06F17/5072

摘要： A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A location is determined for a user defined region on the target device that allows the system to satisfy timing constraints.

摘要翻译： 公开了一种使用可编程逻辑器件（PLD）将系统的组件定位到目标器件上的方法。 确定目标设备上用户定义区域的位置，允许系统满足时序约束。

公开(公告)号：US08434044B1

公开(公告)日：2013-04-30

申请号：US12968128

申请日：2010-12-14

申请人： David Samuel Goldman ,  Bruce B. Pedersen ,  Gabriel Quan ,  Yuen Ho Choi

发明人： David Samuel Goldman ,  Bruce B. Pedersen ,  Gabriel Quan ,  Yuen Ho Choi

IPC分类号： G06F17/50 ,  G06F13/14

CPC分类号： G06F17/5072

摘要： A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.

摘要翻译： 提供了一种可编程芯片设计工具来枚举和指定可编程芯片设计的安全和/或冗余约束。 设计采用高级安全或冗余方案实现，而可编程芯片设计工具则应用该方案同时优化所需度量（逻辑密度，可布线性，时序，功率等）。 提供了一个底层分配方案以及用于输入此分配方案的用户界面组件。

公开(公告)号：US20230333826A1

公开(公告)日：2023-10-19

申请号：US18338236

申请日：2023-06-20

申请人： Michael Kinsner ,  Byron Sinclair ,  Deshanand P. Singh ,  Scott Jeremy Weber ,  Mahesh A. Iyer ,  Chengping Liang ,  Victor Tzi-on Zhang ,  Gabriel Quan

发明人： Michael Kinsner ,  Byron Sinclair ,  Deshanand P. Singh ,  Scott Jeremy Weber ,  Mahesh A. Iyer ,  Chengping Liang ,  Victor Tzi-on Zhang ,  Gabriel Quan

IPC分类号： G06F8/41 ,  G06F8/36

CPC分类号： G06F8/41 ,  G06F8/36

摘要： Systems or methods of the present disclosure may provide a library including multiple regional bits streams that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device. The design may be decomposed into one or more regional bitstreams and stitched to form a larger combined bitstream to be implemented as coarse-grained operations on the integrated circuit device, thereby decreasing compilation time experienced by the designer. The combined bitstreams may be loaded into all or a portion of the integrated circuit device to realize the design. Additionally or alternatively, the integrated circuit device may include a hardened networks-on-chip to improve data routing within the combined bitstream.