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1.发明授权Method and apparatus for placement and routing of partial reconfiguration modules 有权部分重新配置模块的放置和路由的方法和装置公开(公告)号：US08671377B2
公开(公告)日：2014-03-11
申请号：US13040255
申请日：2011-03-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054 , G06F17/5072 , G06F2217/72
摘要： A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
摘要翻译： 用于在目标设备上设计系统的方法包括将目标设备上的资源分配给系统中的静态逻辑模块和部分可重新配置（PR）模块。 其中一个PR模块的实例使用分配的那些资源进行并行布置和路由。 还公开了其他实施例。
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公开(公告)号：US08627254B2
公开(公告)日：2014-01-07
申请号：US13618176
申请日：2012-09-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.
摘要翻译： 介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。 在一种方法中，CAD工具接收到IC参数的值分配。 值分配作为一个值范围输入。 确定I / O块中每个输入/输出（I / O）引脚的最小和最大路径延迟，使得满足接收到的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。 切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。
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公开(公告)号：US20130080987A1
公开(公告)日：2013-03-28
申请号：US13618176
申请日：2012-09-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.
摘要翻译： 介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。 在一种方法中，CAD工具接收到IC参数的值分配。 值分配作为一个值范围输入。 确定I / O块中每个输入/输出（I / O）引脚的最小和最大路径延迟，使得满足接收到的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。 切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。
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4.发明申请Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules 有权部分重新配置模块的放置和路由的方法和装置公开(公告)号：US20120227026A1
公开(公告)日：2012-09-06
申请号：US13040255
申请日：2011-03-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054 , G06F17/5072 , G06F2217/72
摘要： A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
摘要翻译： 用于在目标设备上设计系统的方法包括将目标设备上的资源分配给系统中的静态逻辑模块和部分可重新配置（PR）模块。 其中一个PR模块的实例使用分配的那些资源进行并行布置和路由。 还公开了其他实施例。
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公开(公告)号：US08434044B1
公开(公告)日：2013-04-30
申请号：US12968128
申请日：2010-12-14
CPC分类号： G06F17/5072
摘要： A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.
摘要翻译： 提供了一种可编程芯片设计工具来枚举和指定可编程芯片设计的安全和/或冗余约束。 设计采用高级安全或冗余方案实现，而可编程芯片设计工具则应用该方案同时优化所需度量（逻辑密度，可布线性，时序，功率等）。 提供了一个底层分配方案以及用于输入此分配方案的用户界面组件。
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公开(公告)号：US08296704B1
公开(公告)日：2012-10-23
申请号：US12833797
申请日：2010-07-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.
摘要翻译： 介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。 在一种方法中，CAD工具接收到IC参数的值分配。 值分配作为值分配的范围输入，或作为可能的值分配列表。 此外，该方法包括用于确定I / O块中的每个输入/输出（I / O）引脚的最小和最大路径延迟的操作，使得满足接收的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。 切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。 此外，还包括其他方法操作，用于路由到I / O引脚的路径，以满足实际切换时间，并为IC创建满足实际切换时间的设计。
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7.发明授权Preventing information leakage between components on a programmable chip in the presence of faults 有权在存在故障的情况下防止可编程芯片上的组件之间的信息泄漏公开(公告)号：US08356358B2
公开(公告)日：2013-01-15
申请号：US12631588
申请日：2009-12-04
CPC分类号： G06F21/76 , G06F17/5054 , G06F17/5077 , G06F2217/70 , G09C1/00
摘要： Mechanisms are provided to prevent information leakage between components implemented on a programmable chip such as a Field Programmable Gate Array (FPGA). An automated routing algorithm is effective at enforcing security restrictions with minimal input form the user while providing efficient utilization of the device. Compatible sets of signals are identified and locked, and reservations of routing resources are generated. Remaining signals are rerouted until all signal constraints are met. Specified security constraints with one or more security levels and one or more secure regions may be applied through iterations of the automated routing mechanism.
摘要翻译： 提供了用于防止在诸如现场可编程门阵列（FPGA）的可编程芯片上实现的组件之间的信息泄漏的机制。 自动路由算法在提供对设备的有效利用的同时以用户的最小输入来实施安全限制是有效的。 识别和锁定兼容的信号集，并生成路由资源的预留。 剩余信号被重新路由，直到满足所有信号约束。 可以通过迭代自动路由机制来应用具有一个或多个安全级别和一个或多个安全区域的指定的安全约束。
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8.发明申请PREVENTING INFORMATION LEAKAGE BETWEEN COMPONENTS ON A PROGRAMMABLE CHIP IN THE PRESENCE OF FAULTS 有权防止故障存在时可编程芯片组件之间的信息泄漏公开(公告)号：US20110138223A1
公开(公告)日：2011-06-09
申请号：US12631588
申请日：2009-12-04
IPC分类号： G06F11/07
CPC分类号： G06F21/76 , G06F17/5054 , G06F17/5077 , G06F2217/70 , G09C1/00
摘要： Mechanisms are provided to prevent information leakage between components implemented on a programmable chip such as a Field Programmable Gate Array (FPGA). An automated routing algorithm is effective at enforcing security restrictions with minimal input form the user while providing efficient utilization of the device. Compatible sets of signals are identified and locked, and reservations of routing resources are generated. Remaining signals are rerouted until all signal constraints are met. Specified security constraints with one or more security levels and one or more secure regions may be applied through iterations of the automated routing mechanism.
摘要翻译： 提供了用于防止在诸如现场可编程门阵列（FPGA）的可编程芯片上实现的组件之间的信息泄漏的机制。 自动路由算法在提供对设备的有效利用的同时以用户的最小输入来实施安全限制是有效的。 识别和锁定兼容的信号集，并生成路由资源的预留。 剩余信号被重新路由，直到满足所有信号约束。 可以通过迭代自动路由机制来应用具有一个或多个安全级别和一个或多个安全区域的指定的安全约束。
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