公开(公告)号：US6156595A

公开(公告)日：2000-12-05

申请号：US168518

申请日：1998-10-08

申请人： Shigeki Sawada

发明人： Shigeki Sawada

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/8238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method for producing a bipolar transistor and an MOS transistor of the present invention includes the steps of: forming a first insulation film in an MOS transistor region where the MOS transistor is to be formed and in a bipolar transistor region where the bipolar transistor is to be formed; forming a first conductive film and a second insulation film on the first insulation film; and removing the second insulation film, the first conductive film and the first insulation film from the bipolar transistor region.

摘要翻译： 本发明的双极晶体管和MOS晶体管的制造方法包括以下步骤：在要形成MOS晶体管的MOS晶体管区域中形成第一绝缘膜，在双极晶体管的双极晶体管区域 形成; 在所述第一绝缘膜上形成第一导电膜和第二绝缘膜; 以及从双极晶体管区域去除第二绝缘膜，第一导电膜和第一绝缘膜。

公开(公告)号：US6001676A

公开(公告)日：1999-12-14

申请号：US9273

申请日：1998-01-20

申请人： Shigeki Sawada ,  Takashi Furuta

发明人： Shigeki Sawada ,  Takashi Furuta

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/8238

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

摘要： Formed on a p-type semiconductor substrate are bipolar transistors and CMOS transistors. A bipolar transistor has a base extraction electrode a side-surface of which is covered with an oxide layer, a silicon nitride layer, and a polysilicon layer. A CMOS transistor has a gate electrode a side-surface of which is covered with an oxide layer, a silicon nitride layer, and a side-wall layer. The silicon nitride layer on the side-surface of the base extraction electrode is formed by the same fabrication step that the silicon nitride layer on the side-surface of the gate electrode is formed.

摘要翻译： 在p型半导体衬底上形成双极晶体管和CMOS晶体管。 双极晶体管具有基极引出电极，其侧表面被氧化物层，氮化硅层和多晶硅层覆盖。 CMOS晶体管具有其氧化物层，氮化硅层和侧壁层的侧表面的栅电极。 通过与形成栅电极侧面的氮化硅层相同的制造工序，形成基极引出电极侧面上的氮化硅层。

公开(公告)号：US5591656A

公开(公告)日：1997-01-07

申请号：US454410

申请日：1995-05-30

申请人： Shigeki Sawada

发明人： Shigeki Sawada

IPC分类号： H01L27/02 ,  H01L21/265

CPC分类号： H01L27/0233 ,  Y10S148/01

摘要： A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an IIL to be an injector are formed on a P-type silicon substrate 1 by self-aligned and integrated. The emitter leading-out part opening of the superhigh speed vertical NPN transistor and the collector leading-out part opening of the vertical NPN transistor having a reverse direction structure are self-aligned to the base leading-out electrode. In the epitaxial layer, the P-type intrinsic base layer of superhigh speed vertical NPN transistor is formed by impurity diffusion from the emitter leading-out electrode formed of polysilicon film, and the P-type base layer of the vertical NPN transistor having a reverse direction structure is formed by ion implantation. By thus forming the superhigh speed vertical NPN transistor having a reverse direction structure in self-aligned process, the superhigh speed vertical NPN transistor of self-aligned type and IIL device may be integrated on a same chip. Besides, by forming the intrinsic base layer of the vertical NPN transistor having a reverse direction structure deeper in junction than the base layer formed by impurity diffusion from the polysilicon emitter electrode for the superhigh speed NPN transistor of self-aligned type, the low concentration epitaxial layer part beneath the intrinsic base layer for composing the emitter of the vertical NPN transistor having a reverse direction structure may be made smaller, thereby avoiding lowering of the current gain of the vertical NPN transistor having a reverse direction structure and lowering of high speed operation of IIL device accompanying accumulation of minority carrier.

摘要翻译： 在P型硅衬底1上通过自身形成具有超薄基极的超高速垂直晶体管，具有用于组成IIL的反向结构的垂直NPN晶体管和类似地构成作为注入器的IIL的横向PNP晶体管 调整和整合。 超高速垂直NPN晶体管的发射极引出部分开路和具有反向结构的垂直NPN晶体管的集电极导出部分开口与基极引出电极自对准。 在外延层中，通过从由多晶硅膜形成的发射极引出电极的杂质扩散形成超高速垂直NPN晶体管的P型本征基极层，垂直NPN晶体管的P型基极层具有反向 方向结构由离子注入形成。 通过这样形成在自对准工艺中具有反向结构的超高速垂直NPN晶体管，自对准型和IIL器件的超高速垂直NPN晶体管可以集成在同一芯片上。 此外，通过形成垂直NPN晶体管的本征基极层，其具有比用于自对准型超高速NPN晶体管的多晶硅发射极电极形成的基底层更接近结构的反向结构，低浓度外延 可以使具有反向结构的垂直NPN晶体管的发射极的本征基极层下方的层部分变小，从而避免具有反向结构的垂直NPN晶体管的电流增益的降低和高速运行的降低 IIL装置伴随着少数载体的积累。