公开(公告)号：US20040155299A1

公开(公告)日：2004-08-12

申请号：US10701696

申请日：2003-11-04

发明人： Arup Bhattacharyya

IPC分类号： H01L029/76

CPC分类号： H01L29/66742 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/7317 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7842 ,  H01L29/78687 ,  Y10S148/009

摘要： The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

摘要翻译： 本发明包括BIFETRAM设备。 这样的器件包括与三维堆叠配置的场效应晶体管（FET）组合的双极晶体管。 存储器件可以结合在绝缘体上半导体（SOI）结构中。 双极器件的基极区域可以物理地和电连接到FET的源极/漏极区域之一，以用作存储单元的存储节点。 SOI结构的半导体材料可以包括Si / Ge，并且FET的有源区可以延伸到Si / Ge中。 SOI结构可以形成在任何多个基底上，包括例如半导体材料，玻璃，氧化铝，二氧化硅，金属和/或塑料。

公开(公告)号：US5904519A

公开(公告)日：1999-05-18

申请号：US879320

申请日：1997-06-19

申请人： Masaru Wakabayashi

发明人： Masaru Wakabayashi

IPC分类号： H01L21/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/8238

CPC分类号： H01L21/8249 ,  Y10S148/009

摘要： A method of manufacturing a semiconductor device made up of a Bi-CMOS integrated circuit with the performance of MOS and bipolar elements enhanced. A semiconductor substrate surface is selectively oxidized to divide surface into a bipolar element forming area and a MOS element forming area. Next, the entire substrate surface is oxidized to form an oxide film 9, after which high-density ions are implanted into a collector leading area. Then, driving-in of the collector leading area is performed by performing heat treatment in an oxidizing atmosphere while forming an oxide film 9b on the collector leading area and another oxide film 9a on the MOS element forming area. Subsequently, the oxide film is etched all over the semiconductor substrate surface by the thickness of the oxide film 9a to expose the semiconductor substrate surface of the MOS element forming area. Lastly, the substrate surface is entirely oxidized to form a gate insulation film thinner than the oxide film 9.

摘要翻译： 一种制造由具有MOS和双极性元件的性能的Bi-CMOS集成电路构成的半导体器件的方法。 选择性地氧化半导体衬底表面以将表面分成双极元件形成区域和MOS元件形成区域。 接下来，将整个基板表面氧化以形成氧化膜9，之后将高密度离子注入集电极引导区域。 然后，通过在氧化气氛中进行热处理，同时在集电极引导区域上形成氧化膜9b和在MOS元件形成区域上形成另一个氧化物膜9a来进行集电极引导区的导入。 随后，氧化膜在半导体衬底表面上被氧化膜9a的厚度蚀刻，以暴露MOS元件形成区域的半导体衬底表面。 最后，基板表面被完全氧化以形成比氧化膜9薄的栅极绝缘膜。

公开(公告)号：US5838048A

公开(公告)日：1998-11-17

申请号：US915327

申请日：1997-08-20

申请人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

发明人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/51 ,  H01L27/02 ,  H01L29/68

CPC分类号： H01L29/513 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/518 ,  Y10S148/009

摘要： A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

摘要翻译： 在硅衬底上形成氧化硅膜和多晶硅膜，并且被选择性地蚀刻以在要形成发射极的区域中形成接触孔。 将多晶硅膜放置在衬底上，并且将两个多晶硅膜图案化以形成由掺杂有砷的两个多晶硅膜制成的发射极电极和栅极电极。 砷从发射电极的多晶硅膜扩散到硅衬底中以形成具有高浓度且浅的N +发射极层。 因此，可以防止栅极绝缘膜的污染，并且可以形成具有高性能的双极晶体管，例如高电流放大因子等。

公开(公告)号：US5804476A

公开(公告)日：1998-09-08

申请号：US758848

申请日：1996-12-02

申请人： Young-Soo Jang

发明人： Young-Soo Jang

IPC分类号： H01L27/06 ,  H01L21/265 ,  H01L21/8249 ,  H01L29/772 ,  H01L21/8238

CPC分类号： H01L21/8249 ,  Y10S148/009 ,  Y10S148/124

摘要： A BiCMOS device and a manufacturing method thereof according to the present invention has a gate insulating layer of NMOSFET having non-uniform thickness. The thickness of the end portion of the gate insulating layer, which is near LDD regions, is thicker than that of center portion. Therefore, the GIDL and the gate-drain overlap capacitance is reduced. In addition, in case of the bipolar transistor of the BiCMOS device, there exists a portion of an oxide film below the side portion of the emitter polysilicon and over the side portions of the emitter region. Since this structure serves as a gate of field effect transistor, N- channel is produced in the emitter region when the emitter-base junction is reversely biased and thus the hot carrier reliability is improved.

摘要翻译： 根据本发明的BiCMOS器件及其制造方法具有不均匀厚度的NMOSFET栅极绝缘层。 靠近LDD区域的栅极绝缘层的端部的厚度比中心部的厚度厚。 因此，GIDL和栅 - 漏重叠电容减小。 此外，在BiCMOS器件的双极晶体管的情况下，在发射极多晶硅的侧部和发射极区的侧部之上存在氧化膜的一部分。 由于该结构用作场效应晶体管的栅极，当发射极 - 基极结反向偏置时，在发射极区域中产生N沟道，因此提高了热载流子的可靠性。

公开(公告)号：US5691224A

公开(公告)日：1997-11-25

申请号：US668655

申请日：1996-06-25

申请人： Juergen Foerstner ,  Myriam Combes ,  Arlette Marty-Blavier ,  Guy Hautekiet

发明人： Juergen Foerstner ,  Myriam Combes ,  Arlette Marty-Blavier ,  Guy Hautekiet

IPC分类号： H01L27/06 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/70

CPC分类号： H01L21/8249 ,  H01L21/74 ,  Y10S148/009

摘要： A method of manufacturing an integrated circuit having a buried layer of a low doped type of conductivity (2) and a buried layer of a highly doped type of the same conductivity (3) by masking a substrate (1) so as to define open areas on the substrate where it is desired to provide the two buried layers and doping the open areas of the substrate with a low concentration of dopants to form the low doped type of buried layer (2) is formed. Then one open area where the low doped type of buried layer (2) is formed is masked and the other open area is doped with a high concentration of dopants to form the highly doped type of buried layer (3).

摘要翻译： 一种制造集成电路的方法，该集成电路具有通过掩蔽衬底（1）而具有低掺杂类型的导电性（2）的掩埋层和具有相同导电性（3）的高掺杂型掩埋层，以限定开放区域 在需要提供两个掩埋层的衬底上，并且形成具有低浓度掺杂剂以形成低掺杂型掩埋层（2）的衬底的开放区域。 然后，在其中形成低掺杂型掩埋层（2）的一个开放区域被掩蔽，并且另一个开放区域掺杂有高浓度的掺杂剂以形成高掺杂型掩埋层（3）。

公开(公告)号：US5652154A

公开(公告)日：1997-07-29

申请号：US679379

申请日：1996-07-08

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： H01L21/8249 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L21/265

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

摘要： In a method for manufacturing a "BiCMOS" semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electrode 112c. A heat treatment is performed to form an emitter diffused region 113. Phosphorus and boron are selectively implanted with a low impurity concentration, respectively, to form a LDD N.sup.- region 114 and a LDD P.sup.- region 115. Thereafter, a side wall 116 is formed, and boron is implanted into areas B and C so as to form P.sup.+ source/drain regions 117 and a graft base region 18, respectively. Phosphorus is implanted to form N.sup.+ source/drain regions 119.

摘要翻译： 在“BiCMOS”半导体集成电路的制造方法中，在半导体基板上生长栅极氧化膜110和多晶硅膜，在磷掺杂后，对多晶硅膜进行图案化，形成栅电极112a，112b，发射极 电极112c。 进行热处理以形成发射极扩散区域113.分别以低杂质浓度选择性地注入磷和硼以形成LDD N-区域114和LDD P-区域115.此后，侧壁116为 并且将硼注入到区域B和C中，以分别形成P +源极/漏极区域117和移植物基底区域18。 植入磷以形成N +源极/漏极区域119。

公开(公告)号：US5643810A

公开(公告)日：1997-07-01

申请号：US688998

申请日：1996-08-01

申请人： Young-Soo Jang

发明人： Young-Soo Jang

IPC分类号： H01L21/334 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/265

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  Y10S148/009 ,  Y10S438/92

摘要： Methods of forming BiCMOS semiconductor devices include steps for forming bird's beak shaped oxide extensions between the gate electrodes and drain and source regions of CMOS devices to inhibit drain leakage currents and reduce gate-to-drain capacitance. These methods also include steps for forming bird's beak shaped oxide extensions at the emitter-base junctions of BJTs to reduce hot carrier induced P-N junction breakdown. A preferred method includes the steps of forming a gate electrode of a field effect transistor on a face of a semiconductor substrate and then forming self-aligned source and drain regions in the substrate using the gate electrode as a mask. A first conductive layer is then formed on the source and drain regions and used to diffuse dopants into the source and drain regions to increase the conductivity therein. Simultaneously with this diffusion step, the ends of the gate electrode and the first conductive layer are oxidized to form first bird's beak shaped oxide extensions between the gate electrode and the source and drain regions. These first bird's beak shaped oxide extensions are preferably formed to reduce drain leakage currents and gate-to-source capacitance by, among other things, reducing the electric field between the drain-side end of the gate electrode and the drain region. The first conductive layer can also be etched back into discrete intermediate source and drain contact regions to facilitate the subsequent formation of source and drain electrodes in electrical contact with the source and drain regions. Similar steps can also be performed to simultaneously form bipolar junction transistors adjacent the field effect transistors.

摘要翻译： 形成BiCMOS半导体器件的方法包括在CMOS器件的栅极电极和漏极和源极区域之间形成鸟嘴形氧化物延伸的步骤，以抑制漏极漏电流并降低栅极 - 漏极电容。 这些方法还包括在BJT的发射极 - 基极结处形成鸟喙状氧化物延伸的步骤，以减少热载体诱导的P-N结击穿。 优选的方法包括以下步骤：在半导体衬底的表面上形成场效应晶体管的栅极，然后使用栅电极作为掩模在衬底中形成自对准的源区和漏区。 然后在源极和漏极区域上形成第一导电层，并且用于将掺杂剂扩散到源极和漏极区域中以增加其中的导电性。 与该扩散步骤同时，栅电极和第一导电层的端部被氧化，以在栅电极和源漏区之间形成第一鸟喙形氧化物延伸。 这些第一鸟喙形氧化物延伸部优选地被形成为通过减少栅极电极和漏极区域的漏极侧端部之间的电场来减少漏极漏电流和栅极至源极电容。 第一导电层还可以被回蚀刻成离散的中间源极和漏极接触区域，以便随后形成与源极和漏极区域电接触的源极和漏极。 也可以执行类似的步骤以同时形成与场效应晶体管相邻的双极结型晶体管。

公开(公告)号：US5512497A

公开(公告)日：1996-04-30

申请号：US272312

申请日：1994-07-08

申请人： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

发明人： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/265 ,  H01L21/8238

CPC分类号： H01L21/28026 ,  H01L21/28525 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

摘要翻译： 公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

公开(公告)号：US5506156A

公开(公告)日：1996-04-09

申请号：US279087

申请日：1994-07-22

申请人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

发明人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L21/8249 ,  Y10S148/009

摘要： A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.

摘要翻译： 半导体器件包括多个第一导电类型的半导体区域和第二导电类型的多个半导体区域。 具有第二导电类型的沟道的AMOS晶体管形成在第一导电类型的半导体区域中，并且在第二导电类型的半导体区域中形成具有第一导电类型的沟道的双极晶体管和MOS晶体管。 第一导电类型的半导体区域由半导体层构成，其中杂质浓度随着其表面的深度而减小，第一导电类型的第一掩埋层形成在半导体衬底中，并且杂质 在厚度方向上的浓度分布具有单个峰值，并且形成在半导体层和第一掩埋层之间的第一导电类型的第二掩埋层，并且其中厚度方向上的杂质浓度分布具有单峰 值。 在外延生长处理和场氧化处理完成之后，通过离子注入法形成第一和第二掩埋层。

公开(公告)号：US5455189A

公开(公告)日：1995-10-03

申请号：US203236

申请日：1994-02-28

申请人： Michael J. Grubisich

发明人： Michael J. Grubisich

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L21/265

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  Y10S148/009 ,  Y10S148/01

摘要： In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other. A heavy implant of the second conductivity type creates a field implant region around each transistor. Around the bipolar transistor, the field implant region meets the channel stop region. Field oxide is grown over the field implant region by LOCOS process. A base region is formed inside the guard ring. Other features and embodiments are described in the specification, the drawings and the claims.

摘要翻译： 在双极或BiCMOS工艺中，在第二导电类型的轻掺杂衬底中形成第一导电类型的重掺杂掩埋层和第二导电类型的重掺杂沟道阻挡区。 生长第一导电类型的轻掺杂外延层。 第一导电类型的注入在双极晶体管有源区周围产生保护环，并且还在有源区内部产生较高掺杂的集电极区域。 在BiCMOS工艺中，在CMOS阱的形成期间，双极晶体管上的氮化硅掩模抑制了外延层的氧化和掩埋层的氧化增强的扩散。 结果，可以使外延层更薄，从而降低集电极电阻。 可以形成MOS晶体管阱，而不需要下层掩埋层，简化工艺并将双极和MOS晶体管特性互相解耦。 第二导电类型的重注入在每个晶体管周围产生场注入区域。 在双极晶体管周围，场注入区域与沟道停止区域相交。 场氧化物通过LOCOS工艺在场注入区域上生长。 在保护环内部形成基部区域。 在说明书，附图和权利要求中描述了其它特征和实施例。