公开(公告)号：US20190317731A1

公开(公告)日：2019-10-17

申请号：US16454369

申请日：2019-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Suvam Nandi ,  Pooja Sundar ,  Jaiganesh Balakrishnan

IPC: G06F7/523 ,  G06F7/50 ,  H03D7/16

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

公开(公告)号：US10050636B2

公开(公告)日：2018-08-14

申请号：US15389236

申请日：2016-12-22

Applicant: Texas Instruments Incorporated

Inventor： Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Nagarajan Viswanathan ,  Pooja Sundar

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms.

公开(公告)号：US20180019732A1

公开(公告)日：2018-01-18

申请号：US15645647

申请日：2017-07-10

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sthanunathan Ramakrishnan ,  Pooja Sundar ,  Sashidharan Venkatraman

IPC: H03H17/02 ,  G06F7/544 ,  H03H17/00 ,  G06F5/01 ,  H03M1/12

CPC classification number: H03H17/0219 ,  G06F5/01 ,  G06F7/5443 ,  H03H17/0045 ,  H03H17/06 ,  H03M1/0626 ,  H03M1/12 ,  H03M1/1215

Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.