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公开(公告)号：US11239833B2
公开(公告)日：2022-02-01
申请号：US17071302
申请日：2020-10-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Ram Narayan Krishna Nama Mony , Pooja Sundar
Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
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公开(公告)号：US11736138B2
公开(公告)日：2023-08-22
申请号：US17493943
申请日：2021-10-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Pooja Sundar , Harshavardhan Adepu , Wenjing Lu , Yeswanth Guntupalli
CPC classification number: H04B1/40 , H04B1/0075
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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公开(公告)号：US11489517B2
公开(公告)日：2022-11-01
申请号：US17558794
申请日：2021-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Ram Narayan Krishna Nama Mony , Pooja Sundar
Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
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公开(公告)号：US11171681B2
公开(公告)日：2021-11-09
申请号：US17072104
申请日：2020-10-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Pooja Sundar , Harshavardhan Adepu , Wenjing Lu , Yeswanth Guntupalli
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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公开(公告)号：US20200301666A1
公开(公告)日：2020-09-24
申请号：US16852710
申请日：2020-04-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Suvam Nandi , Pooja Sundar , Jaiganesh Balakrishnan
Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
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Patent Agency Ranking
公开(公告)号：US10277202B2
公开(公告)日：2019-04-30
申请号：US15645647
申请日：2017-07-10
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh Balakrishnan , Sthanunathan Ramakrishnan , Pooja Sundar , Sashidharan Venkatraman
Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.
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公开(公告)号：US10372415B2
公开(公告)日：2019-08-06
申请号：US15587096
申请日：2017-05-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Suvam Nandi , Pooja Sundar , Jaiganesh Balakrishnan
Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
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公开(公告)号：US20190214972A1
公开(公告)日：2019-07-11
申请号：US16299299
申请日：2019-03-12
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh Balakrishnan , Sthanunathan Ramakrishnan , Pooja Sundar , Sashidharan Venkatraman
CPC classification number: H03H17/0219 , G06F5/01 , G06F7/5443 , H03H17/0045 , H03H17/06 , H03M1/0626 , H03M1/12 , H03M1/1215
Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.
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公开(公告)号：US20170324421A1
公开(公告)日：2017-11-09
申请号：US15389236
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Sthanunathan Ramakrishnan , Nagarajan Viswanathan , Pooja Sundar
CPC classification number: H03M1/0617 , H03M1/1009 , H03M1/1042 , H03M1/1215 , H03M1/1245
Abstract: Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms.
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公开(公告)号：US11029919B2
公开(公告)日：2021-06-08
申请号：US16852710
申请日：2020-04-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Suvam Nandi , Pooja Sundar , Jaiganesh Balakrishnan
Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
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