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    Serial interface devices, systems and methods
    11.
    发明授权
    Serial interface devices, systems and methods 有权
    串行接口设备，系统和方法

    公开(公告)号：US08464145B2

    公开(公告)日：2013-06-11

    申请号：US12838035

    申请日：2010-07-16

    Applicant: Edward L. Grivna ,  Gabriel Li ,  Thinh Tran

    Inventor： Edward L. Grivna ,  Gabriel Li ,  Thinh Tran

    IPC: G06F11/00 ,  H03M13/00

    CPC classification number: G06F13/4291 ,  G06F11/1016

    Abstract: A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.

    Abstract translation: 串行接口设备包括多个串行链路连接，其至少在不同的串行链路连接上接收地址值和至少一个错误检测码（EDC），从至少地址值生成的EDC，地址值的串行链路连接以及 EDC彼此分开操作; 和多个输出串行链路，输出串行链路中的至少第一个输出从对应于地址值的存储器位置读取的数据值，以及至少第二个输出串行链路，与第一个输出串行链路不同，并且与第一个串行链路分开运行 为从内存位置读取的数据值生成的EDC值。

    Memory device and method
    12.
    发明授权
    Memory device and method 有权
    内存设备和方法

    公开(公告)号：US08149643B2

    公开(公告)日：2012-04-03

    申请号：US12288984

    申请日：2008-10-23

    Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

    Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

    IPC: G11C8/00

    CPC classification number: G11C8/18 ,  G11C8/12

    Abstract: A memory device and method may include separating alternating read and write accesses to different banks of a memory device.

    Abstract translation: 存储器件和方法可以包括将交替的读和写访问分离到存储器件的不同组。

    Memory system and method
    13.
    发明授权
    Memory system and method 有权
    内存系统和方法

    公开(公告)号：US08095747B2

    公开(公告)日：2012-01-10

    申请号：US12239532

    申请日：2008-09-26

    Applicant: Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

    Inventor： Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

    IPC: G06F12/00

    CPC classification number: G06F13/28

    Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

    Abstract translation: 在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控​​制器。 配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。 配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

    MEMORY SYSTEM AND METHOD
    15.
    发明申请
    MEMORY SYSTEM AND METHOD 有权
    记忆系统和方法

    公开(公告)号：US20100082861A1

    公开(公告)日：2010-04-01

    申请号：US12239532

    申请日：2008-09-26

    Applicant: Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

    Inventor： Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

    IPC: G06F13/42 ,  G06F13/40 ,  G06F13/28

    CPC classification number: G06F13/28

    Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

    Abstract translation: 在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控​​制器。 配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。 配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

    FLUID TIMELINE SOCIAL NETWORK
    16.
    发明申请
    FLUID TIMELINE SOCIAL NETWORK 审中-公开

    公开(公告)号：US20200371654A1

    公开(公告)日：2020-11-26

    申请号：US16988413

    申请日：2020-08-07

    Applicant: Thinh Tran

    Inventor： Thinh Tran

    IPC: G06F3/0485 ,  G06Q50/00 ,  G06F40/106 ,  G06F16/9537

    Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

    MEMORY DEVICE AND METHOD
    17.
    发明申请
    MEMORY DEVICE AND METHOD 有权
    存储器件和方法

    公开(公告)号：US20120014202A1

    公开(公告)日：2012-01-19

    申请号：US13245856

    申请日：2011-09-26

    Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

    Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

    IPC: G11C8/18

    CPC classification number: G11C8/18 ,  G11C8/12

    Abstract: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period

    Abstract translation: 在相同时间段中多次访问存储器件的方法可以包括在第一次访问顺序中，与第一时钟周期的第一部分同步地开始对多个存储体之一的访问操作，并开始访问 与第一时钟周期的第二部分同步地操作到多个存储体中的另一个存储体，每个存储体具有单独的访问电路; 并且连续访问之间的时间比对于相同银行的背对背访问的访问速度更快; 其中在访问操作期间，在相同的时间段内访问每个存储体的存储位置

    Area efficient and fast static random access memory circuit and method
    18.
    发明授权
    Area efficient and fast static random access memory circuit and method 失效
    区域高效快速静态随机存取电路及方法

    公开(公告)号：US07684257B1

    公开(公告)日：2010-03-23

    申请号：US11958215

    申请日：2007-12-17

    Applicant: Christopher Lee ,  Thinh Tran ,  Joseph Tzou ,  Morgan Whately

    Inventor： Christopher Lee ,  Thinh Tran ,  Joseph Tzou ,  Morgan Whately

    IPC: G11C7/00 ,  G11C7/10

    CPC classification number: G11C7/1006 ,  G11C11/413

    Abstract: Disclosed is an accumulation memory circuit for providing a fast read, modify, and write operation in a single clock cycle time. The memory circuit is configured to read data stored in the memory device at an address. The memory circuit includes a reconfigurable adder unit generating read, accumulate and write output in a single clock cycle. The memory circuit is further configured to minimize data overflow. A high speed accumulation method comprises resetting a memory circuit; reading from an address of the memory circuit; performing internal addition within the memory circuit and rewriting into the address of the memory circuit in a single clock cycle.

    Abstract translation: 公开了一种用于在单个时钟周期时间内提供快速读取，修改和写入操作的累加存储器电路。 存储器电路被配置为以地址读取存储在存储器件中的数据。 存储器电路包括可重构加法器单元，其在单个时钟周期内产生读取，累加和写入输出。 存储器电路还被配置为最小化数据溢出。 高速累积方法包括：重置存储器电路; 从存储器电路的地址读取; 在存储器电路内执行内部加法，并在单个时钟周期内重写到存储器电路的地址。

    Fluid timeline social network
    20.
    发明授权
    Fluid timeline social network 有权

    公开(公告)号：US10747415B2

    公开(公告)日：2020-08-18

    申请号：US16549859

    申请日：2019-08-23

    Applicant: Thinh Tran

    Inventor： Thinh Tran

    IPC: G06F3/0485 ,  G06Q50/00 ,  G06F16/9537 ,  G06F40/106 ,  H04L12/58

    Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

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