公开(公告)号：US07892895B2

公开(公告)日：2011-02-22

申请号：US11207634

申请日：2005-08-19

申请人： Shien-Yang Wu ,  Shi-Bai Chen

发明人： Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L21/82

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity, preferably a p-type impurity. The anode and the portion of the link adjoining the anode are doped with a second impurity, preferably an n-type impurity. The junction of the first impurity and the second impurity in the link forms a p-n junction diode. A conductive layer, such as a silicide layer, is formed over the p-n junction diodes. In an alternative embodiment, a plurality of p-n junction diodes may be formed in each link. One or more contacts may be formed to provide electrical contact to the cathode and the anode.

摘要翻译： 用于提供具有p-n结二极管的电熔丝的系统和方法。 优选实施例包括阴极，阳极和形成在阴极和阳极之间的一个或多个连接。 邻接连接的阴极和阴极部分掺杂有第一杂质，优选p型杂质。 阳极和邻接阳极的连接部分掺杂有第二杂质，优选为n型杂质。 连接中的第一杂质和第二杂质的结形成p-n结二极管。 在p-n结二极管上形成诸如硅化物层的导电层。 在替代实施例中，可以在每个链路中形成多个p-n结二极管。 可以形成一个或多个触点以提供与阴极和阳极的电接触。

公开(公告)号：US07456066B2

公开(公告)日：2008-11-25

申请号：US11592291

申请日：2006-11-03

申请人： Shien-Yang Wu

发明人： Shien-Yang Wu

IPC分类号： H01L21/8234

CPC分类号： H01L21/823468 ,  H01L21/823864

摘要： MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.

公开(公告)号：US07271431B2

公开(公告)日：2007-09-18

申请号：US10877441

申请日：2004-06-25

申请人： Chuan-Yi Lin ,  Shien-Yang Wu ,  Yee-Chia Yeo

发明人： Chuan-Yi Lin ,  Shien-Yang Wu ,  Yee-Chia Yeo

IPC分类号： H01L29/76

CPC分类号： H01L21/823481 ,  H01L21/823475

摘要： According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy substrate is selectively etched. The photo resist is then removed. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. The source and drain are formed on the surface of said substrate and on opposite sides of the gate. Silicide is formed on the gate electrode, source, and drain. A layer of inter-level dielectric is then formed. A contact opening and metal wiring are then formed.

摘要翻译： 根据本发明，集成电路包括半导体衬底上的隔离场区域。 栅极电介质形成在衬底的表面上。 栅电极形成在栅极电介质上。 形成覆盖有源区的光致抗蚀剂。 虚拟图案被有选择地蚀刻。 选择性地蚀刻虚设衬底。 然后去除光刻胶。 在栅电极和栅极电介质的相对侧壁上形成一对间隔物。 源极和漏极形成在所述衬底的表面上和栅极的相对侧上。 在栅电极，源极和漏极上形成硅化物。 然后形成层间电介质层。 然后形成接触开口和金属布线。

公开(公告)号：US20050237841A1

公开(公告)日：2005-10-27

申请号：US10829689

申请日：2004-04-22

申请人： Shien-Yang Wu ,  Jhon-Jhy Liaw

发明人： Shien-Yang Wu ,  Jhon-Jhy Liaw

IPC分类号： G11C7/00 ,  G11C17/18

CPC分类号： G11C17/18

摘要： A programming method for fuse cells. A core circuit is applied with a first power voltage. The fuse cell includes an electrical fuse element connected to a common node, and a driver device connected between the electrical fuse element and a ground node. The ground node has a ground voltage. The fuse cell has a control gate for controlling current through the electrical fuse element. In program mode, a second power voltage is applied to the common node, a first control voltage is applied to the control gate of a selected fuse cell and a second control voltage is applied to the control gate of an unselected fuse cell. In read mode, the first power voltage is applied to the common node. The second power voltage exceeds the first power voltage. The second control voltage exceeds the ground voltage. The second control voltage is also lower than the first control voltage.

摘要翻译： 一种熔丝电池的编程方法。 核心电路采用第一电源电压。 熔丝单元包括连接到公共节点的电熔丝元件和连接在电熔丝元件和接地节点之间的驱动器件。 接地节点具有接地电压。 熔丝单元具有用于控制通过电熔丝元件的电流的控制栅极。 在编程模式下，向公共节点施加第二电源电压，将第一控制电压施加到所选择的熔丝单元的控制栅极，并且将第二控制电压施加到未选择的熔丝单元的控制栅极。 在读取模式下，第一个电源电压被施加到公共节点。 第二电源电压超过第一电源电压。 第二个控制电压超过接地电压。 第二控制电压也低于第一控制电压。

公开(公告)号：US20050218475A1

公开(公告)日：2005-10-06

申请号：US10805747

申请日：2004-03-22

申请人： Shien-Yang Wu ,  Shi-Bai Chen

发明人： Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L23/62 ,  H01L27/10

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A fuse comprises a silicide element disposed above a substrate, a first terminal contact coupled to a first end of the silicide element, and a first metal line disposed above the silicide element and coupled to the first terminal contact. The fuse further comprises a plurality of second terminal contacts coupled to a second end of the silicide element, and a second metal line disposed above the silicide element and coupled to the plurality of second terminal contacts. The silicide element has a sufficient width that a programming potential applied across the first and second metal lines causes a discontinuity in the first terminal contact.

摘要翻译： 熔丝包括设置在衬底上的硅化物元件，耦合到硅化物元件的第一端的第一端子触点和设置在硅化物元件上方并耦合到第一端子触点的第一金属线。 熔丝还包括耦合到硅化物元件的第二端的多个第二端子触点，以及设置在硅化物元件上方并耦合到多个第二端子触点的第二金属线。 硅化物元件具有足够的宽度，使得施加在第一和第二金属线上的编程电位导致第一端子触点中的不连续性。

公开(公告)号：US08969999B2

公开(公告)日：2015-03-03

申请号：US13283127

申请日：2011-10-27

申请人： Minchang Liang ,  Shien-Yang Wu ,  Wei-Chang Kung

发明人： Minchang Liang ,  Shien-Yang Wu ,  Wei-Chang Kung

IPC分类号： H01L27/12 ,  H01L23/52 ,  H01L23/525 ,  H01L27/112 ,  H01L29/78 ,  H01L27/105

CPC分类号： H01L21/823431 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/823481 ,  H01L23/5256 ,  H01L27/1052 ,  H01L27/11206 ,  H01L29/1087 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse device and method for fabricating the fuse device is disclosed. An exemplary fuse device includes a first contact and a second contact coupled with a metal-semiconductor alloy layer, wherein the metal-semiconductor alloy layer extends continuously between the first contact and the second contact. The metal-semiconductor alloy layer is disposed over an epitaxial layer that is disposed over a fin structure of a substrate.

摘要翻译： 公开了一种用于制造熔丝器件的保险丝装置和方法。 示例性熔丝器件包括第一触点和与金属 - 半导体合金层耦合的第二触点，其中金属 - 半导体合金层在第一触点和第二触点之间连续延伸。 金属 - 半导体合金层设置在设置在基板的翅片结构之外的外延层上。

公开(公告)号：US20130105895A1

公开(公告)日：2013-05-02

申请号：US13283127

申请日：2011-10-27

申请人： Minchang Liang ,  Shien-Yang Wu ,  Wei-Chang Kung

发明人： Minchang Liang ,  Shien-Yang Wu ,  Wei-Chang Kung

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L21/823431 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/823481 ,  H01L23/5256 ,  H01L27/1052 ,  H01L27/11206 ,  H01L29/1087 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse device and method for fabricating the fuse device is disclosed. An exemplary fuse device includes a first contact and a second contact coupled with a metal-semiconductor alloy layer, wherein the metal-semiconductor alloy layer extends continuously between the first contact and the second contact. The metal-semiconductor alloy layer is disposed over an epitaxial layer that is disposed over a fin structure of a substrate.

摘要翻译： 公开了一种用于制造熔丝器件的保险丝装置和方法。 示例性熔丝器件包括第一触点和与金属 - 半导体合金层耦合的第二触点，其中金属 - 半导体合金层在第一触点和第二触点之间连续延伸。 金属 - 半导体合金层设置在设置在基板的翅片结构之外的外延层上。

公开(公告)号：US08174091B2

公开(公告)日：2012-05-08

申请号：US12503641

申请日：2009-07-15

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US07952142B2

公开(公告)日：2011-05-31

申请号：US12253755

申请日：2008-10-17

申请人： Shien-Yang Wu

发明人： Shien-Yang Wu

IPC分类号： H01L27/088

CPC分类号： H01L21/823468 ,  H01L21/823864

摘要： MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.

摘要翻译： 提供包括多个宽度偏移间隔物的MOSFET栅极结构。 第一和第二栅极结构形成在半导体衬底上。 在第一栅极结构的两侧形成一对第一偏移间隔物。 每个第一偏移间隔物包括具有第一介电层的第一氧化硅层。 在第二栅极结构的两侧形成一对第二偏移间隔物。 每个第二偏移间隔物包括具有覆盖的第二电介质层的第二氧化硅层。 离子注入的掺杂区域分别形成在与第一和第二偏移间隔物相邻的半导体衬底中，以形成第一和第二MOSFET器件。 每个第一偏移间隔物的最大宽度与第二偏移间隔物的最大宽度不同。 第一氧化硅层比第二氧化硅层薄。

公开(公告)号：US07109564B2

公开(公告)日：2006-09-19

申请号：US10805747

申请日：2004-03-22

申请人： Shien-Yang Wu ,  Shi-Bai Chen

发明人： Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A fuse comprises a silicide element disposed above a substrate, a first terminal contact coupled to a first end of the silicide element, and a first metal line disposed above the silicide element and coupled to the first terminal contact. The fuse further comprises a plurality of second terminal contacts coupled to a second end of the silicide element, and a second metal line disposed above the silicide element and coupled to the plurality of second terminal contacts. The silicide element has a sufficient width that a programming potential applied across the first and second metal lines causes a discontinuity in the first terminal contact.

摘要翻译： 熔丝包括设置在衬底上的硅化物元件，耦合到硅化物元件的第一端的第一端子触点和设置在硅化物元件上方并耦合到第一端子触点的第一金属线。 熔丝还包括耦合到硅化物元件的第二端的多个第二端子触点，以及设置在硅化物元件上方并耦合到多个第二端子触点的第二金属线。 硅化物元件具有足够的宽度，使得施加在第一和第二金属线上的编程电位导致第一端子触点中的不连续性。