公开(公告)号：US20230402288A1

公开(公告)日：2023-12-14

申请号：US17857158

申请日：2022-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yeh-Sheng Lin ,  Chang-Mao Wang ,  Chun-Chi Yu ,  Chung-Yi Chiu

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31111 ,  H01L21/76802 ,  H01L21/31144

Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

公开(公告)号：US20200273714A1

公开(公告)日：2020-08-27

申请号：US16286495

申请日：2019-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ying Lai ,  Chang-Mao Wang ,  Hsin-Yu Hsieh

IPC: H01L21/311 ,  H01L21/768

Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.