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    RESISTIVE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    11.
    发明公开
    RESISTIVE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230354724A1

    公开(公告)日：2023-11-02

    申请号：US17750425

    申请日：2022-05-23

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L49/02

    CPC classification number: H01L45/1253 ,  H01L45/146 ,  H01L28/24 ,  H01L45/1625 ,  H01L45/1616

    Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.

    Semiconductor device and method for forming the same
    12.
    发明授权
    Semiconductor device and method for forming the same 有权

    公开(公告)号：US11765915B2

    公开(公告)日：2023-09-19

    申请号：US17870814

    申请日：2022-07-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H10B63/00 ,  H10N70/00

    CPC classification number: H10B63/80 ,  H10N70/063 ,  H10N70/826

    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

    RESISTIVE RANDOM-ACCESS MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    13.
    发明申请
    RESISTIVE RANDOM-ACCESS MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230020564A1

    公开(公告)日：2023-01-19

    申请号：US17404934

    申请日：2021-08-17

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.

    Method for manufacturing a resistive random access memory structure
    14.
    发明授权
    Method for manufacturing a resistive random access memory structure 有权

    公开(公告)号：US11538990B2

    公开(公告)日：2022-12-27

    申请号：US17371376

    申请日：2021-07-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A method for forming a resistive random access memory structure. The resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    15.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220102429A1

    公开(公告)日：2022-03-31

    申请号：US17084609

    申请日：2020-10-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.

    RRAM AND FABRICATING METHOD OF THE SAME
    16.
    发明申请
    RRAM AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20240431219A1

    公开(公告)日：2024-12-26

    申请号：US18224054

    申请日：2023-07-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: An RRAM includes a bottom electrode, a resistive switching layer, a top electrode and a cap layer stacked from bottom to top. The cap layer includes a top surface. A first spacer contacts a first sidewall of the bottom electrode, and a second sidewall of the resistive switching layer. A second spacer contacts the first spacer and contacts a third spacer of the top electrode. A thickness of the first spacer is greater of a thickness of the second spacer. The first spacer and the second spacer do not cover the topmost surface of the cap layer.

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