公开(公告)号：US20200035492A1

公开(公告)日：2020-01-30

申请号：US16592773

申请日：2019-10-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ming-Te Wei ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Chien-Ting Ho

IPC: H01L21/033 ,  H01L21/02 ,  H01L27/108 ,  H01L21/3105 ,  H01L21/027

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

公开(公告)号：US09929162B1

公开(公告)日：2018-03-27

申请号：US15456564

申请日：2017-03-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin ,  Chien-Ting Ho

IPC: H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: A semiconductor device include a substrate including at least a memory cell region formed thereon, an isolation mesh formed on the substrate; and a plurality of storage node contact plugs. The semiconductor device includes a plurality of memory cells formed in the memory cell region. The isolation mesh includes a plurality of essentially homogeneous dielectric sidewalls and a plurality of first apertures defined by the dielectric sidewalls. The storage node contact plugs are respectively formed in the first apertures, and electrically connected to the memory cells respectively.

公开(公告)号：US20190341252A1

公开(公告)日：2019-11-07

申请号：US15968680

申请日：2018-05-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ming-Te Wei ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Chien-Ting Ho

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.