公开(公告)号：US20220392798A1

公开(公告)日：2022-12-08

申请号：US17888502

申请日：2022-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

公开(公告)号：US11515159B2

公开(公告)日：2022-11-29

申请号：US17137320

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/47 ,  H01L21/311

Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.

公开(公告)号：US20220178992A1

公开(公告)日：2022-06-09

申请号：US17114515

申请日：2020-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yi-Hsiu Chen ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: G01R31/28

Abstract: A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.

公开(公告)号：US20210151321A1

公开(公告)日：2021-05-20

申请号：US17137320

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/47 ,  H01L21/311

Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.