公开(公告)号：US20190109202A1

公开(公告)日：2019-04-11

申请号：US16212626

申请日：2018-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/4975 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.

公开(公告)号：US10170573B1

公开(公告)日：2019-01-01

申请号：US15730748

申请日：2017-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  I-Fan Chang ,  Jui-Ming Yang ,  Wen-Tsung Chang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a metal gate on the substrate, and a first inter-layer dielectric (ILD) layer around the metal gate. A top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate. A mask layer is disposed in the recessed region. A void is formed in the mask layer within the recessed region. A second ILD layer is disposed on the mask layer and the first ILD layer. A contact hole extends into the second ILD layer and the mask layer. The contact hole exposes the top surface of the metal gate and communicates with the void. A conductive layer is disposed in the contact hole and the void.

公开(公告)号：US20190043725A1

公开(公告)日：2019-02-07

申请号：US15688852

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/28167 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.