公开(公告)号：US20230102936A1

公开(公告)日：2023-03-30

申请号：US17515563

申请日：2021-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

公开(公告)号：US20220013648A1

公开(公告)日：2022-01-13

申请号：US16936442

申请日：2020-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.

公开(公告)号：US11088271B2

公开(公告)日：2021-08-10

申请号：US16691621

申请日：2019-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L21/308 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US20210134993A1

公开(公告)日：2021-05-06

申请号：US16691621

申请日：2019-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US20190027602A1

公开(公告)日：2019-01-24

申请号：US15668719

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen ,  Ting-Hsuan Kang ,  Ren-Yu He ,  Hung-Wen Huang ,  Chi-Hsiao Chen ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

公开(公告)号：US12132095B2

公开(公告)日：2024-10-29

申请号：US18129099

申请日：2023-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/66

CPC classification number: H01L29/66545

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.

公开(公告)号：US11239327B2

公开(公告)日：2022-02-01

申请号：US16513699

申请日：2019-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/40 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.

公开(公告)号：US11127838B2

公开(公告)日：2021-09-21

申请号：US16701051

申请日：2019-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/66

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

公开(公告)号：US10861974B2

公开(公告)日：2020-12-08

申请号：US16361231

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

公开(公告)号：US20200220011A1

公开(公告)日：2020-07-09

申请号：US16812358

申请日：2020-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region. The fin structure extends along a first direction and the dummy gate extends along a second direction. The first direction is not parallel with the second direction.