公开(公告)号：US20180358453A1

公开(公告)日：2018-12-13

申请号：US15642360

申请日：2017-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Wen Huang ,  Kai-Lin Lee ,  Ren-Yu He ,  Chi-Hsiao Chen ,  Ting-Hsuan Kang ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/66977 ,  H01L21/28088 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

Abstract: The present invention provides a method of making a tunneling effect transistor (TFET), the method includes: a substrate is provided, having a fin structure disposed thereon, the fin structure includes a first conductive type, a dielectric layer is then formed on the substrate and on the fin structure, a gate trench is formed in the dielectric layer, and a first work function metal layer is formed in the gate trench, the first work function metal layer defines at least a left portion, a right portion and a central portion, an etching process is performed to remove the central portion of the first work function metal layer, and to form a recess between the left portion and the right portion of the first work function metal layer, afterwards, a second work function metal layer is formed and filled in the recess.

公开(公告)号：US10229995B2

公开(公告)日：2019-03-12

申请号：US15668719

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen ,  Ting-Hsuan Kang ,  Ren-Yu He ,  Hung-Wen Huang ,  Chi-Hsiao Chen ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

公开(公告)号：US20190027602A1

公开(公告)日：2019-01-24

申请号：US15668719

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen ,  Ting-Hsuan Kang ,  Ren-Yu He ,  Hung-Wen Huang ,  Chi-Hsiao Chen ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

公开(公告)号：US20190172949A1

公开(公告)日：2019-06-06

申请号：US16252521

申请日：2019-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen ,  Ting-Hsuan Kang ,  Ren-Yu He ,  Hung-Wen Huang ,  Chi-Hsiao Chen ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.