公开(公告)号：US20200034200A1

公开(公告)日：2020-01-30

申请号：US16048178

申请日：2018-07-27

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Jayneel GANDHI ,  Aasheesh KOLLI ,  Pratap SUBRAHMANYAM

IPC: G06F9/50 ,  G06F15/173 ,  G06F9/455 ,  G06F12/0891

Abstract: Disclosed is a method for performing write-back operations to maintain coherence of remote memories in a memory pool. When a local application makes a request for a page of memory that is in the memory pool but not local, a device obtains the page through its RDMA facility and thereafter keeps track of the page for any changes made by the application to the page by storing the page locally and monitoring cache coherency events of cache lines that make up the page. If a requested page become dirty, then periodically the dirty cache lines of the dirty page are written back to the remote memory from which the pages were obtained. In addition, all dirty cache lines are written back when the local memory storing the page becomes full or the application closes a region containing the page.

公开(公告)号：US20200034175A1

公开(公告)日：2020-01-30

申请号：US16048182

申请日：2018-07-27

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Jayneel GANDHI ,  Aasheesh KOLLI ,  Pratap SUBRAHMANYAM

IPC: G06F9/455 ,  G06F12/0891

Abstract: A virtual machine running on a source host is live migrated to a destination host. The source host includes a first processing node with a first processing hardware and a first memory, and a second processing node with a second processing hardware and a second memory. While the virtual machine is running on the first processing hardware, the second processing hardware tracks cache lines of the first processing hardware that become dirty as a result of write operations performed on one or more memory pages of the virtual machine. The dirty cache lines are copied to the destination host in units of a cache line or groups of cache lines.

公开(公告)号：US20230028825A1

公开(公告)日：2023-01-26

申请号：US17531582

申请日：2021-11-19

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM

IPC: G06F8/656 ,  G06F9/38 ,  G06F9/30 ,  G06F9/455 ,  G06F13/16

Abstract: A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.

公开(公告)号：US20200242036A1

公开(公告)日：2020-07-30

申请号：US16256571

申请日：2019-01-24

Applicant: VMware, Inc.

Inventor： Aasheesh KOLLI ,  Irina CALCIU ,  Jayneel GANDHI ,  Pratap SUBRAHMANYAM

IPC: G06F12/0831 ,  G06F12/109 ,  G06F12/0817 ,  G06F11/07 ,  G06F9/50

Abstract: Disclosed is a technique in which an application can record changes it makes to physical memory. In the technique, the application specifies a virtual memory region which is converted to a plurality of cache lines, each of which is monitored for changes by a device connected to a coherence interconnect coupled to the processor caches. The application sends a start signal to start the logging process and an end signal to stop the process. During the logging process, when a change occurs to one of the cache lines, an undo entry corresponding to the change is created and entered into a transaction log residing in persistent memory. The transaction log containing the undo entries makes the set of changes recorded in the transaction log atomic. If a failure occurs, the recorded changes can be undone as if they never occurred.

公开(公告)号：US20200241978A1

公开(公告)日：2020-07-30

申请号：US16256567

申请日：2019-01-24

Applicant: VMware, Inc.

Inventor： Aasheesh KOLLI ,  Irina CALCIU ,  Jayneel GANDHI ,  Pratap SUBRAHMANYAM

IPC: G06F11/14

Abstract: A module for rewriting application code as a failure-atomic transaction is disclosed. An application delineates a code fragment that is to become a failure-atomic transaction by writing a tx_begin( ) and tx_end( ) functions into its code. A module detects the tx_begin( ) and tx_end( ) functions and rewrites the code fragment as a failure-atomic transaction. The rewritten code is then available to be executed by the application. The rewritten code stores values and locations of stores to persistent memory locations so that the transaction can be either undone or redone in the case of an application error or a power failure. If the transaction is an undo type of transaction, the application can be rolled back to a state prior to the failure. If the transaction is a redo type of transaction, the application can be advanced to a correct state after the error.

公开(公告)号：US20200034294A1

公开(公告)日：2020-01-30

申请号：US16048186

申请日：2018-07-27

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Jayneel GANDHI ,  Aasheesh KOLLI ,  Pratap SUBRAHMANYAM

IPC: G06F12/0815 ,  G06F12/0862 ,  G06F12/1009 ,  G06F9/455

Abstract: Disclosed are embodiments for running an application on a local processor when the application is dependent on pages not locally present but contained in a remote host. The system is informed that the pages on which the application depends are locally present. While running, the application encounters a cache miss and a cache line satisfying the miss from the remote host is obtained and provided to the application. Alternatively, the page containing the cache line satisfying the miss is obtained and the portion of the page not including the cache line is stored locally while the cache line is provided to the application. The cache miss is discovered by monitoring coherence events on a coherence interconnect connected to the local processor. In some embodiments, the cache misses are tracked and provide a way to predict a set of pages to be pre-fetched in anticipation of the next cache misses.

公开(公告)号：US20190129716A1

公开(公告)日：2019-05-02

申请号：US15796635

申请日：2017-10-27

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Jayneel GANDHI ,  Pradeep FERNANDO ,  Aasheesh KOLLI

IPC: G06F9/30 ,  G06F9/46 ,  G06F12/0804 ,  G06F12/0868 ,  G06F11/14

CPC classification number: G06F9/3004 ,  G06F3/067 ,  G06F9/30087 ,  G06F9/466 ,  G06F11/1471 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F2212/1032 ,  G06F2212/214

Abstract: The disclosure provides an approach for atomically executing computer instructions by a CPU of a computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM). The approach generally includes reading an instruction within a section of code designated as an HTM transaction, determining whether the instruction causes a data conflict with another thread, and copying cache lines from memory into a cache of the CPU. The approach further includes marking the copied cache lines as transactional, processing the instruction to create a persistent log within non-volatile memory, and unmarking the copied cache lines from transactional, to non-transactional.