公开(公告)号：US10929295B2

公开(公告)日：2021-02-23

申请号：US16255432

申请日：2019-01-23

Applicant: VMware, Inc.

Inventor： Jayneel Gandhi ,  Pratap Subrahmanyam ,  Irina Calciu ,  Aasheesh Kolli

IPC: G06F12/00 ,  G06F12/0853 ,  G06F12/1045 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/1009

Abstract: Described herein is a method for tracking changes made by an application. Embodiments include determining, by a processor, a write-back of a cache line from a hardware unit associated with a socket of a plurality of sockets to a page table entry of a page table in a memory location associated with the processor. Embodiments include adding, by the processor, the cache line to a list of dirty cache lines. Embodiments include, for each respective cache line in the list of dirty cache lines, identifying, by the processor, a memory location associated with a respective socket of the plurality of sockets corresponding to the respective cache line and updating, by the processor, an entry of a page table replica at the memory location based on the respective cache line.

公开(公告)号：US10922128B1

公开(公告)日：2021-02-16

申请号：US16721646

申请日：2019-12-19

Applicant: VMware, Inc.

Inventor： Gerd Zellweger ,  Lalith Suresh ,  Jayneel Gandhi ,  Amy Tai

IPC: G06F9/54 ,  G06F9/48

Abstract: Techniques for efficiently managing the interruption of user-level critical sections are provided. In certain embodiments, a physical CPU of a computer system can execute a critical section of a user-level thread of an application, where program code for the critical section is marked with CPU instruction(s) indicating that the critical section should be executed atomically. The physical CPU can detect, while executing the critical section, an event to be handled by an OS kernel of the computer system and upon detecting the event, revert changes performed within the critical section. The physical CPU can then invoke a trap handler of the OS kernel, and in response the OS kernel can invoke a user-level handler of the application with information including (1) the identity of the user-level thread, (2) an indication of the event, (3) the physical CPU state upon detecting the event, and (4) an indication that the user-level thread was interrupted while in the critical section.

公开(公告)号：US10761984B2

公开(公告)日：2020-09-01

申请号：US16048186

申请日：2018-07-27

Applicant: VMware, Inc.

Inventor： Irina Calciu ,  Jayneel Gandhi ,  Aasheesh Kolli ,  Pratap Subrahmanyam

IPC: G06F9/455 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/1009

Abstract: Disclosed are embodiments for running an application on a local processor when the application is dependent on pages not locally present but contained in a remote host. The system is informed that the pages on which the application depends are locally present. While running, the application encounters a cache miss and a cache line satisfying the miss from the remote host is obtained and provided to the application. Alternatively, the page containing the cache line satisfying the miss is obtained and the portion of the page not including the cache line is stored locally while the cache line is provided to the application. The cache miss is discovered by monitoring coherence events on a coherence interconnect connected to the local processor. In some embodiments, the cache misses are tracked and provide a way to predict a set of pages to be pre-fetched in anticipation of the next cache misses.

公开(公告)号：US10430186B2

公开(公告)日：2019-10-01

申请号：US15796635

申请日：2017-10-27

Applicant: VMware, Inc.

Inventor： Irina Calciu ,  Jayneel Gandhi ,  Pradeep Fernando ,  Aasheesh Kolli

IPC: G06F3/06 ,  G06F9/30 ,  G06F11/14 ,  G06F12/0804 ,  G06F12/0868 ,  G06F9/46

Abstract: The disclosure provides an approach for atomically executing computer instructions by a CPU of a computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM). The approach generally includes reading an instruction within a section of code designated as an HTM transaction, determining whether the instruction causes a data conflict with another thread, and copying cache lines from memory into a cache of the CPU. The approach further includes marking the copied cache lines as transactional, processing the instruction to create a persistent log within non-volatile memory, and unmarking the copied cache lines from transactional, to non-transactional.