公开(公告)号：US11461050B2

公开(公告)日：2022-10-04

申请号：US17153265

申请日：2021-01-20

Applicant: VMware, Inc.

Inventor： Amy Tai ,  Michael Wei

IPC: G06F3/06

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enforcing a decay policy for a data object. One of the methods includes receiving a request to store a data object in a storage device; obtaining a user policy identifying a lifetime of the data object; determining, using the lifetime of the data object, a voltage policy for a plurality of memory cells of the storage device, wherein: each of the plurality of memory cells will store one or more bits of the data object; the voltage policy identifies a voltage to provide each memory cell; and an expected time at which raw bit errors of the data object will cause the data object to decay is equal to a time point identified by the lifetime of the data object; and storing the data object in the storage device according to the determined voltage policy.

公开(公告)号：US20220083468A1

公开(公告)日：2022-03-17

申请号：US17021872

申请日：2020-09-15

Applicant: VMware, Inc.

Inventor： Michael Wei ,  Nadav Amit ,  Amy Tai

IPC: G06F12/0802 ,  G06F9/4401

Abstract: Techniques for consolidating shared state for translation lookaside buffer (TLB) shootdowns are provided. In one set of embodiments, an operating system (OS) kernel of a computer system can co-locate, in a system memory of the computer system, a plurality of shared data accessed by first and second processing cores of the computer system for performing a translation lookaside buffer (TLB) shootdown of the first processing core by the second processing core, where the co-locating allows the plurality of shared data to occupy a single cache line when brought from the system memory into a CPU (central processing unit) cache of the first or second processing core. This can include, e.g., (1) co-locating a lazy mode indicator and a call function queue (CFQ) head element of the first processing core, such that these two data components occupy the same cache line, and (2) co-locating a TLB flush info entry and a call function data (CFD) entry created by the second processing core at the time of initiating the TLB shootdown, such that these two data components occupy the same cache line.

公开(公告)号：US11068422B1

公开(公告)日：2021-07-20

申请号：US16804480

申请日：2020-02-28

Applicant: VMware, Inc.

Inventor： Amy Tai ,  Igor Smolyar ,  Dan Tsafrir ,  Michael Wei ,  Nadav Amit

IPC: G06F13/24 ,  G06F3/06 ,  G06F13/10

Abstract: Described herein are embodiments that adaptively reduce the number of interrupts that occur between a device controller and a computer system. Device commands are submitted to the controller by an operating system on behalf of an application. The device performs the received commands and indicates command completions to the controller. A counter counts completions, and if the count exceeds a threshold number, the controller generates an interrupt to the computer system. If the count is greater than zero and the timeout interval has expired, then the controller generates an interrupt to the computer system. In some embodiments, the application attaches flags to one of the commands indicating that an interrupt relating to completion of the flagged command should be generated as soon as possible or that an interrupt relating to completion of all commands prior to and including the flagged command should be generated as soon as possible.

公开(公告)号：US20220229590A1

公开(公告)日：2022-07-21

申请号：US17153265

申请日：2021-01-20

Applicant: VMware, Inc.

Inventor： Amy Tai ,  Michael Wei

IPC: G06F3/06

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enforcing a decay policy for a data object. One of the methods includes receiving a request to store a data object in a storage device; obtaining a user policy identifying a lifetime of the data object; determining, using the lifetime of the data object, a voltage policy for a plurality of memory cells of the storage device, wherein: each of the plurality of memory cells will store one or more bits of the data object; the voltage policy identifies a voltage to provide each memory cell; and an expected time at which raw bit errors of the data object will cause the data object to decay is equal to a time point identified by the lifetime of the data object; and storing the data object in the storage device according to the determined voltage policy.

公开(公告)号：US11341051B2

公开(公告)日：2022-05-24

申请号：US17021872

申请日：2020-09-15

Applicant: VMware, Inc.

Inventor： Michael Wei ,  Nadav Amit ,  Amy Tai

IPC: G06F12/08 ,  G06F12/0802 ,  G06F9/4401

Abstract: Techniques for consolidating shared state for translation lookaside buffer (TLB) shootdowns are provided. In one set of embodiments, an operating system (OS) kernel of a computer system can co-locate, in a system memory of the computer system, a plurality of shared data accessed by first and second processing cores of the computer system for performing a translation lookaside buffer (TLB) shootdown of the first processing core by the second processing core, where the co-locating allows the plurality of shared data to occupy a single cache line when brought from the system memory into a CPU (central processing unit) cache of the first or second processing core. This can include, e.g., (1) co-locating a lazy mode indicator and a call function queue (CFQ) head element of the first processing core, such that these two data components occupy the same cache line, and (2) co-locating a TLB flush info entry and a call function data (CFD) entry created by the second processing core at the time of initiating the TLB shootdown, such that these two data components occupy the same cache line.

公开(公告)号：US10922128B1

公开(公告)日：2021-02-16

申请号：US16721646

申请日：2019-12-19

Applicant: VMware, Inc.

Inventor： Gerd Zellweger ,  Lalith Suresh ,  Jayneel Gandhi ,  Amy Tai

IPC: G06F9/54 ,  G06F9/48

Abstract: Techniques for efficiently managing the interruption of user-level critical sections are provided. In certain embodiments, a physical CPU of a computer system can execute a critical section of a user-level thread of an application, where program code for the critical section is marked with CPU instruction(s) indicating that the critical section should be executed atomically. The physical CPU can detect, while executing the critical section, an event to be handled by an OS kernel of the computer system and upon detecting the event, revert changes performed within the critical section. The physical CPU can then invoke a trap handler of the OS kernel, and in response the OS kernel can invoke a user-level handler of the application with information including (1) the identity of the user-level thread, (2) an indication of the event, (3) the physical CPU state upon detecting the event, and (4) an indication that the user-level thread was interrupted while in the critical section.

公开(公告)号：US20230089659A1

公开(公告)日：2023-03-23

申请号：US17478063

申请日：2021-09-17

Applicant: VMware, Inc.

Inventor： Ali Najafi ,  Michael Wei ,  Andreas Georg Nowatzyk ,  Amy Tai

IPC: H04J3/06 ,  G06F11/30 ,  G06F1/14

Abstract: Described herein are systems, methods, and software to manage time calibration associated with an oscillator of a computing system. In one example, a computing system monitors clock cycles for an oscillator on the computing system, receives timing messages from a server, and calculates the frequency of the oscillator at intervals based on the monitored clock cycles and timing messages. The computing system further identifies a temperature from a temperature sensor at each of the intervals and generates a function to demonstrate frequency of the oscillator versus temperatures from the temperature sensor based on the identified temperatures and frequencies at the intervals.

公开(公告)号：US11321242B2

公开(公告)日：2022-05-03

申请号：US17021834

申请日：2020-09-15

Applicant: VMware, Inc.

Inventor： Michael Wei ,  Nadav Amit ,  Amy Tai

IPC: G06F12/1027 ,  G06F12/0804 ,  G06F9/48 ,  G06F12/1009

Abstract: Techniques for implementing early acknowledgement for translation lookaside buffer (TLB) shootdowns are provided. In one set of embodiments, a first (i.e., remote) processing core of a computer system can receive an inter-processor interrupt (IPI) from a second (i.e., initiator) processing core of the computer system for performing a TLB shootdown of the first processing core. Upon receiving the IPI, an interrupt handler of the first processing core can communicate an acknowledgement to the second processing core that the TLB of the first processing core has been flushed, prior to actually flushing the TLB.

公开(公告)号：US20220083476A1

公开(公告)日：2022-03-17

申请号：US17021834

申请日：2020-09-15

Applicant: VMware, Inc.

Inventor： Michael Wei ,  Nadav Amit ,  Amy Tai

IPC: G06F12/1027 ,  G06F12/0804 ,  G06F12/1009 ,  G06F9/48

Abstract: Techniques for implementing early acknowledgement for translation lookaside buffer (TLB) shootdowns are provided. In one set of embodiments, a first (i.e., remote) processing core of a computer system can receive an inter-processor interrupt (IPI) from a second (i.e., initiator) processing core of the computer system for performing a TLB shootdown of the first processing core. Upon receiving the IPI, an interrupt handler of the first processing core can communicate an acknowledgement to the second processing core that the TLB of the first processing core has been flushed, prior to actually flushing the TLB.