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公开(公告)号：US12105640B2
公开(公告)日：2024-10-01
申请号：US17945242
申请日：2022-09-15
IPC分类号： G06F12/00 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F12/128 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/603 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.
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公开(公告)号：US12072814B2
公开(公告)日：2024-08-27
申请号：US18309893
申请日：2023-05-01
IPC分类号： G06F12/128 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/603 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.
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公开(公告)号：US20240264952A1
公开(公告)日：2024-08-08
申请号：US18639013
申请日：2024-04-18
IPC分类号： G06F12/128 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/603 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
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公开(公告)号：US12001345B2
公开(公告)日：2024-06-04
申请号：US18340944
申请日：2023-06-26
IPC分类号： G06F12/12 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/121 , G06F12/126 , G06F12/127 , G06F12/128 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
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公开(公告)号：US11940929B2
公开(公告)日：2024-03-26
申请号：US16882234
申请日：2020-05-22
IPC分类号： G06F12/0888 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F12/128 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.
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公开(公告)号：US11901044B2
公开(公告)日：2024-02-13
申请号：US16739784
申请日：2020-01-10
IPC分类号： G16B40/10 , C12Q1/6869 , G06F12/0853 , G16B50/30 , G16B30/00
CPC分类号： G16B40/10 , C12Q1/6869 , G06F12/0853 , G16B30/00 , G16B50/30
摘要： A method for characterizing a sample comprising genetic information, comprising: (i) receiving a plurality of sequencing signals from a sequencing operation for a sample, each of the plurality of sequencing signals representing a genetic sequence; (ii) setting, based on a received sequencing signal, a bit within a bit array to a first value for the received sequencing signal, wherein a set of one or more bits is associated with a unique received sequencing signal; (iii) calculating a rate of change of bits within the bit array as new sequencing signals are received; (iv) comparing the rate of change to a predetermined threshold; and (v) identifying the sequencing operation as insufficient if the rate of change is at or above the predetermined threshold, or identifying the sequencing operation as sufficient if the rate of change is at or below the predetermined threshold.
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公开(公告)号：US20230342305A1
公开(公告)日：2023-10-26
申请号：US18340944
申请日：2023-06-26
IPC分类号： G06F12/0804 , G06F12/0884 , G06F12/0888 , G06F9/54 , G06F12/0811 , G11C7/10 , G06F11/10 , G06F12/12 , G06F12/0806 , G06F12/121 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/126 , G06F12/0891 , G06F12/02 , G06F12/128 , G06F12/0817 , G11C29/42 , G11C29/44 , G06F12/0855 , G06F12/0853 , G06F12/0897 , G06F9/30 , G06F12/0815 , G06F13/16 , G06F12/0802
CPC分类号： G06F12/126 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
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公开(公告)号：US11714760B2
公开(公告)日：2023-08-01
申请号：US16882264
申请日：2020-05-22
IPC分类号： G06F12/0811 , G06F9/30 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/128 , G06F12/0817 , G06F12/0804 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
CPC分类号： G06F12/0811 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/082 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/106 , G11C7/1015 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/608 , G06F2212/6032 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.
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公开(公告)号：US11681636B2
公开(公告)日：2023-06-20
申请号：US16981816
申请日：2019-02-12
申请人： Arm Limited
IPC分类号： G06F12/14 , G06F7/58 , G06F9/30 , G06F21/79 , G06F12/0842 , G06F12/0853 , G06F12/0897 , G06F12/1027
CPC分类号： G06F12/1441 , G06F7/582 , G06F9/3004 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F12/0842 , G06F12/0853 , G06F12/0897 , G06F12/1027 , G06F21/79
摘要： An apparatus has processing circuitry (4); memory access circuitry (15) to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and an instruction decoder (6) responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry (4) to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values.
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公开(公告)号：US11625331B2
公开(公告)日：2023-04-11
申请号：US17229904
申请日：2021-04-14
申请人： FUJITSU LIMITED
IPC分类号： G06F11/10 , G06F12/0875 , G06F12/0846 , G06F11/07 , G06F9/38 , G06F11/30 , G06F9/30 , G06F12/0853
摘要： A cache control apparatus includes a data unit configured to store data on an index-specific basis, a tag unit configured to store, on the index-specific basis, a tag and a flag indicating whether the data has an uncorrectable error, and a control unit configured to refer to the flag, upon detecting a tag hit by performing a read access to the tag unit, to determine whether an uncorrectable error exists in the data corresponding to the tag hit, wherein the control unit performs process scheduling such that the read access to the tag unit and another access to the tag unit are performed simultaneously.
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