公开(公告)号：US07855110B2

公开(公告)日：2010-12-21

申请号：US12169118

申请日：2008-07-08

申请人： Viorel Ontalus ,  Robert Robison

发明人： Viorel Ontalus ,  Robert Robison

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

摘要翻译： 一种FET及其制造方法。 该方法包括在衬底的硅区的顶表面上形成栅电介质层，并在栅电介质层的顶表面上形成栅电极; 在硅区域中形成源极和漏极，并由栅电极下方的沟道区分隔开，源极具有在栅极下延伸的源极延伸，漏极具有在栅电极下延伸的漏极延伸，源极，源极延伸 ，漏极和漏极延伸掺杂第一类型; 以及形成完全在所述源内包含的源极三角洲区域，并且形成完全在所述漏极内包含的漏极三角洲区域，所述δ源极区域和所述δ漏极区域掺杂第二掺杂剂类型，所述第二掺杂剂类型与所述第一掺杂剂类型相反。

公开(公告)号：US08482075B2

公开(公告)日：2013-07-09

申请号：US13468270

申请日：2012-05-10

申请人： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert Robison

发明人： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert Robison

IPC分类号： H01L21/70

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

摘要翻译： 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US20100006952A1

公开(公告)日：2010-01-14

申请号：US12169118

申请日：2008-07-08

申请人： Viorel Ontalus ,  Robert Robison

发明人： Viorel Ontalus ,  Robert Robison

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region of and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

摘要翻译： 一种FET及其制造方法。 该方法包括在衬底的硅区的顶表面上形成栅电介质层，并在栅电介质层的顶表面上形成栅电极; 在栅极电极下方的沟道区域中形成硅区域中的源极和漏极，源极和源极延伸延伸到栅电极下方，漏极延伸延伸到栅电极下方，源极源极 扩展，漏极和漏极延伸掺杂第一类型; 以及形成完全在所述源内包含的源极三角洲区域，并且形成完全在所述漏极内包含的漏极三角洲区域，所述δ源极区域和所述δ漏极区域掺杂第二掺杂剂类型，所述第二掺杂剂类型与所述第一掺杂剂类型相反。