公开(公告)号：US12027217B2

公开(公告)日：2024-07-02

申请号：US17724499

申请日：2022-04-20

Applicant: Winbond Electronics Corp.

Inventor： Kenichi Arakawa

IPC: G11C16/04 ,  G11C16/30

CPC classification number: G11C16/30

Abstract: A semiconductor device and an operation method capable of operating with high reliability are provided. A voltage monitoring circuit (100) of the disclosure includes: a power-on detection part (110) configurated to detect whether a supply voltage (EXVDD) of an external power supply terminal has reached a power-on voltage level; a timer (120) configurated to measure a predetermined time when the power-on voltage level is detected; a through current generation part (130) configurated to generate a through current between the external power supply terminal and GND during a period when the timer (120) measures the predetermined time; and a power-off detection part (140) configurated to detect whether a drop of the supply voltage (EXVDD) has reached a power-off voltage level when the through current is generated.

公开(公告)号：US10672485B2

公开(公告)日：2020-06-02

申请号：US16244128

申请日：2019-01-10

Applicant: Winbond Electronics Corp.

Inventor： Kenichi Arakawa

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C5/14 ,  G11C7/02

Abstract: A semiconductor storage device achieving stabilization of an operating voltage of a selected memory chip. A flash memory device of the disclosure includes a master chip and at least one slave chip. A voltage output portion of a charge pump circuit of the master chip is connected to an internal pad of the master chip, and a voltage output portion of a charge pump circuit of the slave chip is connected to an internal pad of the slave chip, the internal pad of the master chip and the internal pad of the slave chip are connected by a wire. When the mater chip is operated, the charge pump circuit of the master chip is turned off, the charge pump circuit of the slave chip is turned on, and a voltage generated by the charge pump circuit of the slave chip is supplied to the master chip.

公开(公告)号：US20160141039A1

公开(公告)日：2016-05-19

申请号：US14740278

申请日：2015-06-16

Applicant: Winbond Electronics Corp.

Inventor： Kenichi Arakawa

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/16

Abstract: A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit (410) such that the gate voltage follows the voltage of the P-well to be discharged.

Abstract translation: 提供了抑制构成位线选择电路的低电压晶体管的击穿的半导体存储器件。 构成位线选择电路的NAND串单元和晶体管（BLSe，BLso，BIASe，BIASo）形成在P阱中。 在擦除操作期间将晶体管设置为浮置状态。 当擦除电压施加到P阱时，晶体管的电压增加。 当擦除电压从P阱放电时，晶体管的栅极经由放电电路（410）连接到参考电位，使得栅极电压遵循要排出的P阱的电压。

公开(公告)号：US09153335B2

公开(公告)日：2015-10-06

申请号：US14301344

申请日：2014-06-11

Applicant: Winbond Electronics Corp.

Inventor： Hiroki Murakami ,  Kenichi Arakawa

IPC: G11C16/30 ,  G11C16/24 ,  G11C16/28

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/30

Abstract: The invention provides a clamp voltage generating circuit capable of generating a correct clamp voltage. The clamp voltage generating circuit includes an emulate transistor, having a drain coupled to a power source VDD, a source coupled to a node, and a gate coupled to the clamp voltage; a current setting circuit, connected between the node and ground, for setting a current flowing from the node to the ground; a regulator, inputting a feedback voltage from the node and a reference voltage, and outputting a voltage VCLMP. The current setting circuit duplicates a current of a bit line, so that the emulate transistor is similar to a charge transfer transistor.

Abstract translation: 本发明提供一种能产生正确钳位电压的钳位电压发生电路。 钳位电压产生电路包括仿真晶体管，其具有耦合到电源VDD的漏极，耦合到节点的源极和耦合到钳位电压的栅极; 连接在节点和地之间的电流设定电路，用于设定从节点流向地面的电流; 调节器，输入来自节点的反馈电压和参考电压，并输出电压VCLMP。 电流设置电路复制位线的电流，使得仿真晶体管类似于电荷转移晶体管。