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公开(公告)号：US11502680B2
公开(公告)日：2022-11-15
申请号：US17238183
申请日：2021-04-22
Applicant: Winbond Electronics Corp.
Inventor： Kenichi Arakawa
IPC: G06F1/24 , H03K17/22 , H03F3/217 , G06F1/3203
Abstract: A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.
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公开(公告)号：US20190214098A1
公开(公告)日：2019-07-11
申请号：US16244128
申请日：2019-01-10
Applicant: Winbond Electronics Corp.
Inventor： Kenichi Arakawa
Abstract: A semiconductor storage device achieving stabilization of an operating voltage of a selected memory chip. A flash memory device of the disclosure includes a master chip and at least one slave chip. A voltage output portion of a charge pump circuit of the master chip is connected to an internal pad of the master chip, and a voltage output portion of a charge pump circuit of the slave chip is connected to an internal pad of the slave chip, the internal pad of the master chip and the internal pad of the slave chip are connected by a wire. When the mater chip is operated, the charge pump circuit of the master chip is turned off, the charge pump circuit of the slave chip is turned on, and a voltage generated by the charge pump circuit of the slave chip is supplied to the master chip.
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公开(公告)号：US09396803B2
公开(公告)日：2016-07-19
申请号：US14740278
申请日：2015-06-16
Applicant: Winbond Electronics Corp.
Inventor： Kenichi Arakawa
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/16
Abstract: A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit (410) such that the gate voltage follows the voltage of the P-well to be discharged.
Abstract translation: 提供了抑制构成位线选择电路的低电压晶体管的击穿的半导体存储器件。 构成位线选择电路的NAND串单元和晶体管（BLSe，BLso，BIASe，BIASo）形成在P阱中。 在擦除操作期间将晶体管设置为浮置状态。 当擦除电压施加到P阱时，晶体管的电压增加。 当擦除电压从P阱放电时，晶体管的栅极经由放电电路（410）连接到参考电位，使得栅极电压遵循要排出的P阱的电压。
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公开(公告)号：US20220359018A1
公开(公告)日：2022-11-10
申请号：US17724499
申请日：2022-04-20
Applicant: Winbond Electronics Corp.
Inventor： Kenichi Arakawa
IPC: G11C16/30
Abstract: A semiconductor device and an operation method capable of operating with high reliability are provided. A voltage monitoring circuit (100) of the disclosure includes: a power-on detection part (110) configurated to detect whether a supply voltage (EXVDD) of an external power supply terminal has reached a power-on voltage level; a timer (120) configurated to measure a predetermined time when the power-on voltage level is detected; a through current generation part (130) configurated to generate a through current between the external power supply terminal and GND during a period when the timer (120) measures the predetermined time; and a power-off detection part (140) configurated to detect whether a drop of the supply voltage (EXVDD) has reached a power-off voltage level when the through current is generated.
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公开(公告)号：US20150055418A1
公开(公告)日：2015-02-26
申请号：US14301344
申请日：2014-06-11
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami , Kenichi Arakawa
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/28 , G11C16/30
Abstract: The invention provides a clamp voltage generating circuit capable of generating a correct clamp voltage. The clamp voltage generating circuit includes an emulate transistor, having a drain coupled to a power source VDD, a source coupled to a node, and a gate coupled to the clamp voltage; a current setting circuit, connected between the node and ground, for setting a current flowing from the node to the ground; a regulator, inputting a feedback voltage from the node and a reference voltage, and outputting a voltage VCLMP. The current setting circuit duplicates a current of a bit line, so that the emulate transistor is similar to a charge transfer transistor.
Abstract translation: 本发明提供一种能产生正确钳位电压的钳位电压发生电路。 钳位电压产生电路包括仿真晶体管，其具有耦合到电源VDD的漏极，耦合到节点的源极和耦合到钳位电压的栅极; 连接在节点和地之间的电流设定电路，用于设定从节点流向地面的电流; 调节器，输入来自节点的反馈电压和参考电压，并输出电压VCLMP。 电流设置电路复制位线的电流，使得仿真晶体管类似于电荷转移晶体管。
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Patent Agency Ranking
公开(公告)号：US11227658B2
公开(公告)日：2022-01-18
申请号：US16903714
申请日：2020-06-17
Applicant: Winbond Electronics Corp.
Inventor： Kenichi Arakawa , Sho Okabe
Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.
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公开(公告)号：US20210351771A1
公开(公告)日：2021-11-11
申请号：US17238183
申请日：2021-04-22
Applicant: Winbond Electronics Corp.
Inventor： Kenichi Arakawa
IPC: H03K17/22 , G06F1/3203 , H03F3/217
Abstract: A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.
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公开(公告)号：US20190115084A1
公开(公告)日：2019-04-18
申请号：US16111157
申请日：2018-08-23
Applicant: Winbond Electronics Corp.
Inventor： Kenichi Arakawa
IPC: G11C16/26
Abstract: A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170. The memory cell array 110 includes a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data to be programmed to a page selected by the memory cell array 110. The page buffer/sense circuit 170 is arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array 110. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.
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公开(公告)号：US09865358B2
公开(公告)日：2018-01-09
申请号：US15435985
申请日：2017-02-17
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami , Kenichi Arakawa
CPC classification number: G11C16/3445 , G11C16/0416 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.
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公开(公告)号：US09263145B2
公开(公告)日：2016-02-16
申请号：US14537352
申请日：2014-11-10
Applicant: Winbond Electronics Corp.
Inventor： Kenichi Arakawa
CPC classification number: G11C16/26 , G11C7/1051 , G11C11/2273 , G11C13/0007 , G11C13/004 , G11C16/0483 , G11C16/24 , G11C2013/0045 , G11C2013/0054 , G11C2213/82
Abstract: The invention provides a current detection circuit and a semiconductor memory apparatus using the current detection circuit thereof. The current detection circuit is capable of rapidly sensing the current flowing through a tiny bit line structure. A page buffer/sensing circuit of the invention includes: a transistor TP3 pre-charging a node SNS during a pre-charge period and providing a target constant current to the node SNS during a discharge period; a transistor TN3 pre-charging the bit line according to the voltage pre-charged to the node SNS; and a transistor TP2 connected to the node SNS. The transistor TP2 detects whether or not a current larger than the constant current supplied by the transistor TP3 is discharged from the bit line and outputs a detection result to a node SENSE.
Abstract translation: 本发明提供一种使用其电流检测电路的电流检测电路和半导体存储装置。 电流检测电路能够快速检测流过微小位线结构的电流。 本发明的页缓冲/感测电路包括：晶体管TP3在预充电期间预充电节点SNS，并在放电期间向节点SNS提供目标恒定电流; 晶体管TN3根据预先充电到节点SNS的电压对位线进行预充电; 以及连接到节点SNS的晶体管TP2。 晶体管TP2检测从晶体管TP3提供的恒流的电流是否从位线放电，并将检测结果输出到节点SENSE。
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