公开(公告)号：US10204841B1

公开(公告)日：2019-02-12

申请号：US15369545

申请日：2016-12-05

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Raghunandan Chaware

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L21/78

Abstract: A method for fabricating integrated circuit (IC) dies and wafers having such dies, are disclosed herein that leverage temporary connection traces during wafer level testing of the functionality of the IC die. In one example, a wafer includes a plurality of IC dies. At least a first IC die of the plurality of IC dies includes a plurality of micro-bumps and a first temporary connection trace formed on an exterior surface of the die body. The plurality of micro-bumps includes at least a first micro-bump and a second micro-bump. The first temporary connection trace electrically couples the first micro-bump and the second micro-bump.

公开(公告)号：US09865567B1

公开(公告)日：2018-01-09

申请号：US15423303

申请日：2017-02-02

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Ganesh Hariharan ,  Inderjit Singh ,  Amitava Majumdar ,  Glenn O'Rourke

IPC: H01L21/58 ,  H01L25/065 ,  H01L25/00 ,  H01L21/82 ,  H01L21/66 ,  H01L23/00 ,  H01L21/56 ,  H01L25/16

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/82 ,  H01L22/14 ,  H01L22/20 ,  H01L24/17 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/17181

Abstract: An example method of manufacturing a semiconductor assembly includes: forming first integrated circuit (IC) dies and dummy dies; forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites for second IC dies; attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer at the second mounting sites; processing a backside and the top side of the interposer wafer; removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and attaching the second IC dies to the interposer wafer at the exposed second mounting sites.