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公开(公告)号:US20190244925A1
公开(公告)日:2019-08-08
申请号:US16385399
申请日:2019-04-16
发明人: KUAN-YU HUANG , TZU-KAI LAN , SHOU-CHIH YIN , SHU-CHIA HSU , PAI-YUAN LI , SUNG-HUI HUANG , HSIANG-FAN LEE , YING-SHIN HAN
IPC分类号: H01L23/00 , H01L23/498 , H01L21/48 , H01L25/18
CPC分类号: H01L24/17 , H01L21/4853 , H01L23/49816 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L25/03 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/0603 , H01L2224/10126 , H01L2224/10145 , H01L2224/11013 , H01L2224/11502 , H01L2224/11849 , H01L2224/13021 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/14135 , H01L2224/14136 , H01L2224/14177 , H01L2224/14505 , H01L2224/16111 , H01L2224/16112 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/17505 , H01L2224/81191 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2924/15311 , H01L2924/18161 , H01L2924/3841 , H01L2924/014 , H01L2924/00014
摘要: A semiconductor device includes an electronic component, a package, a substrate and a plurality of first conductors and second conductors. The package is over the electronic component. T substrate is between the electronic component and the package. The substrate includes a first portion covered by the package, and a second portion protruding out of an edge of the package and uncovered by the package. The first conductors and second conductors are between and electrically connected to the electronic component and the substrate. A width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors, the first conductors are disposed between the second portion of the substrate and the electronic component, and the second conductors are disposed between the first portion of the substrate and the electronic component.
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公开(公告)号:US20190198067A1
公开(公告)日:2019-06-27
申请号:US16113500
申请日:2018-08-27
发明人: Seon-Kyoo LEE , Dae-Hoon NA , Jeong-Don IHM , Byung-Hoon JEONG , Young-Don CHOI
IPC分类号: G11C7/10 , G11C7/22 , G11C7/06 , H01L25/065
CPC分类号: G11C7/1051 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/1048 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C7/14 , G11C7/222 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48106 , H01L2224/48225 , H01L2224/48227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06586 , H01L2924/15192 , H01L2924/15311
摘要: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.
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公开(公告)号:US20190051612A1
公开(公告)日:2019-02-14
申请号:US15869517
申请日:2018-01-12
发明人: Young-Iyong KIM , Hyun-soo CHUNG , Dong-hyeon JANG
IPC分类号: H01L23/552 , H01L23/00 , H01L23/34 , H01L23/538
CPC分类号: H01L23/552 , H01L23/345 , H01L23/367 , H01L23/4334 , H01L23/5384 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/12105 , H01L2224/13025 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/32145 , H01L2224/32245 , H01L2224/48227 , H01L2224/73204 , H01L2224/73267 , H01L2224/83851 , H01L2224/83862 , H01L2224/83874 , H01L2224/92244 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/3025 , H01L2924/3511 , H01L2224/83 , H01L2924/0665 , H01L2924/069 , H01L2924/0635
摘要: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.
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公开(公告)号:US20180323118A1
公开(公告)日:2018-11-08
申请号:US16019083
申请日:2018-06-26
发明人: Tsung-Ding Wang , An-Jhih Su , Chien Ling Hwang , Jung Wei Cheng , Hsin-Yu Pan , Chen-Hua Yu
IPC分类号: H01L23/04 , H01L23/00 , H01L23/42 , H01L21/56 , H01L23/10 , H01L23/367 , H01L23/498
CPC分类号: H01L23/04 , H01L21/563 , H01L23/10 , H01L23/3675 , H01L23/42 , H01L23/49816 , H01L24/02 , H01L24/05 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L2224/023 , H01L2224/04026 , H01L2224/11616 , H01L2224/14181 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/26145 , H01L2224/2745 , H01L2224/27452 , H01L2224/27462 , H01L2224/27602 , H01L2224/27616 , H01L2224/27622 , H01L2224/29011 , H01L2224/29124 , H01L2224/29138 , H01L2224/29147 , H01L2224/29166 , H01L2224/29181 , H01L2224/29187 , H01L2224/29191 , H01L2224/2929 , H01L2224/29294 , H01L2224/29309 , H01L2224/29387 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/33505 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81815 , H01L2224/83007 , H01L2224/83104 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/83203 , H01L2224/83815 , H01L2224/83855 , H01L2224/83862 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06589 , H01L2924/1434 , H01L2924/15153 , H01L2924/15311 , H01L2924/16152 , H01L2924/163 , H01L2924/3511 , H01L2924/00014 , H01L2924/05032 , H01L2924/00012 , H01L2924/01014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/05442
摘要: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.
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公开(公告)号:US20180294215A1
公开(公告)日:2018-10-11
申请号:US15927115
申请日:2018-03-21
申请人: FUJITSU LIMITED
发明人: Hironori KAWAMINAMI
IPC分类号: H01L23/498 , H01L23/00 , H01L25/00 , H01L25/065 , H01L23/48
CPC分类号: H01L23/49838 , H01L23/481 , H01L23/538 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/131 , H01L2224/16146 , H01L2224/16235 , H01L2224/16237 , H01L2224/171 , H01L2224/17181 , H01L2224/81191 , H01L2224/81986 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2924/15153 , H01L2224/81 , H01L2924/014
摘要: A semiconductor device includes: a first semiconductor chip that includes through electrodes; a second semiconductor chip; and an interposer that has a recessed portion formed in a front surface thereof and includes a first wiring provided under a bottom surface of the recessed portion, in which the first semiconductor chip is fitted in the recessed portion with a chip top surface thereof flipped down to be electrically connected to the first wiring, the second semiconductor chip is connected on the front surface, of the interposer, around the recessed portion, and at the same time, is stacked on the first semiconductor chip in a manner to partially overlap the first semiconductor chip, and is electrically connected to the first semiconductor chip via the through electrodes.
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公开(公告)号:US20180286834A1
公开(公告)日:2018-10-04
申请号:US15476872
申请日:2017-03-31
申请人: INTEL CORPORATION
发明人: Fay HUA , Telesphor KAMGAING , Johanna M. SWAN
CPC分类号: H01L25/0657 , H01L21/022 , H01L23/293 , H01L23/3128 , H01L23/3192 , H01L23/481 , H01L23/64 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/50 , H01L2223/6677 , H01L2224/02311 , H01L2224/02313 , H01L2224/02315 , H01L2224/02372 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/05164 , H01L2224/06181 , H01L2224/16113 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/17181 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01029 , H01L2924/1903 , H01L2924/19041 , H01L2924/19042 , H01L2924/00014
摘要: Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising active elements and a backside opposite the front side. The device includes a dielectric layer on the backside, and a passive component on the dielectric layer on the backside. In certain embodiments, the passive device is formed on a self-assembled monolayer (SAM). Other embodiments are described and claimed.
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公开(公告)号:US10062661B2
公开(公告)日:2018-08-28
申请号:US15628851
申请日:2017-06-21
申请人: Tessera, Inc.
发明人: Hiroaki Sato , Teck-Gyu Kang , Belgacem Haba , Philip R. Osborn , Wei-Shun Wang , Ellis Chau , Ilyas Mohammed , Norihito Masuda , Kazuo Sakuma , Kiyoaki Hashimoto , Kurosawa Inetaro , Tomoyuki Kikuchi
IPC分类号: H01L23/00 , H01L23/13 , H01L23/31 , H01L23/495 , H01L23/498 , H01L25/065 , H01L25/10 , H01L25/16 , H01L27/146 , H01L25/04 , H01L21/56 , H01L23/538
CPC分类号: H01L24/48 , H01L21/56 , H01L23/13 , H01L23/3107 , H01L23/3128 , H01L23/4952 , H01L23/49811 , H01L23/5389 , H01L24/16 , H01L24/45 , H01L24/49 , H01L24/73 , H01L25/043 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L27/14618 , H01L27/14625 , H01L2224/05599 , H01L2224/16145 , H01L2224/16225 , H01L2224/1713 , H01L2224/17179 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45101 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/48091 , H01L2224/48106 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48245 , H01L2224/48247 , H01L2224/48455 , H01L2224/48464 , H01L2224/49105 , H01L2224/49171 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00012 , H01L2924/00014 , H01L2924/01049 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18165 , H01L2924/19107 , H01L2924/00
摘要: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
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公开(公告)号:US20180226390A1
公开(公告)日:2018-08-09
申请号:US15869808
申请日:2018-01-12
发明人: Pil Kyu KANG , Seok Ho KIM , Tae Yeong KIM , Kwang Jin MOON , Ho Jin LEE
IPC分类号: H01L25/00 , H01L25/065 , H01L23/00 , H01L21/768
CPC分类号: H01L25/50 , H01L21/187 , H01L21/76898 , H01L24/80 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/08145 , H01L2224/16145 , H01L2224/16146 , H01L2224/17181 , H01L2224/2929 , H01L2224/293 , H01L2224/73204 , H01L2224/80047 , H01L2224/80048 , H01L2224/8012 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/80986 , H01L2224/9202 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06568 , H01L2225/06593 , H01L2924/3512 , H01L2224/80001 , H01L2224/81 , H01L2924/00014
摘要: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.
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公开(公告)号:US20180226380A1
公开(公告)日:2018-08-09
申请号:US15853456
申请日:2017-12-22
发明人: PO-CHUN LIN , CHIN-LUNG CHU
IPC分类号: H01L25/065 , H01L25/00 , H01L23/498 , H01L23/00 , H01L23/48
CPC分类号: H01L25/0657 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/50 , H01L2224/0401 , H01L2224/05568 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/17181 , H01L2224/81191 , H01L2225/06513 , H01L2225/06544 , H01L2225/06562 , H01L2225/06565 , H01L2924/15311 , H01L2924/157 , H01L2924/15788
摘要: The present disclosure provides a method for preparing a semiconductor apparatus. The semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.
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公开(公告)号:US10037976B2
公开(公告)日:2018-07-31
申请号:US15704720
申请日:2017-09-14
申请人: INTEL CORPORATION
发明人: Sanka Ganesan , Bassam Ziadeh , Nitesh Nimkar
IPC分类号: H01L23/48 , H01L23/52 , H01L25/065 , H01L25/00 , H01L25/03 , H01L25/10 , H01L23/29 , H01L23/00
CPC分类号: H01L25/0657 , H01L23/293 , H01L24/02 , H01L24/03 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/03 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0381 , H01L2224/08225 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/27 , H01L2224/28105 , H01L2224/29006 , H01L2224/2919 , H01L2224/32058 , H01L2224/32105 , H01L2224/32145 , H01L2224/3301 , H01L2224/33106 , H01L2224/73204 , H01L2224/73253 , H01L2224/80903 , H01L2224/81191 , H01L2224/81203 , H01L2224/83102 , H01L2224/83191 , H01L2224/83203 , H01L2224/83855 , H01L2224/92 , H01L2224/9211 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06548 , H01L2225/1023 , H01L2225/1058 , H01L2924/00012 , H01L2924/15311 , H01L2924/18161 , H01L2924/3512 , H01L2924/0665 , H01L2924/014 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.
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