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44 条记录 (耗时 0.028 秒)

    Memory circuit with logic functions
    12.
    发明授权
    Memory circuit with logic functions 失效
    具有逻辑功能的存储电路

    公开(公告)号：US5113487A

    公开(公告)日：1992-05-12

    申请号：US314238

    申请日：1989-02-22

    申请人： Toshihiko Ogura ,  Hiroaki Aotsu ,  Koichi Kimura ,  Hiromichi Enomoto ,  Tadashi Kyoda

    发明人： Toshihiko Ogura ,  Hiroaki Aotsu ,  Koichi Kimura ,  Hiromichi Enomoto ,  Tadashi Kyoda

    IPC分类号： G09G5/393

    CPC分类号： G09G5/393 ,  G09G2340/10

    摘要： In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in a read-modify-write mode can be used commonly.

    摘要翻译： 在具有可操作以读取，写入和保持数据的存储器件的存储器电路以及在从外部提供的第一数据和从存储器件读出的第二数据之间实现计算的操作单元中选择一个操作功能指定数据预设 外部选择器和用于选择外部存在的位写入控制数据中的一个的选择器具有选择控制信号，使得可以通常使用以读 - 修改 - 写入模式操作的帧缓冲存储器。

    Multi-window display control system
    13.
    发明授权
    Multi-window display control system 失效
    多窗口显示控制系统

    公开(公告)号：US4954818A

    公开(公告)日：1990-09-04

    申请号：US920425

    申请日：1986-10-20

    申请人： Keiichi Nakane ,  Tadashi Kuwabara ,  Naoya Ikeda ,  Hiroyuki Koreeda ,  Hiroaki Aotsu ,  Masaki Kawase ,  Yujiro Tatsuno ,  Naomichi Nonaka ,  Kazunari Suzuki

    发明人： Keiichi Nakane ,  Tadashi Kuwabara ,  Naoya Ikeda ,  Hiroyuki Koreeda ,  Hiroaki Aotsu ,  Masaki Kawase ,  Yujiro Tatsuno ,  Naomichi Nonaka ,  Kazunari Suzuki

    IPC分类号： G09G5/14

    CPC分类号： G09G5/14

    摘要： A central processing unit, a main memory for storing graphic or character data, an external memory, an input device for inputting the graphic or character data, a shared memory for temporarily storing the graphic or character data read by the central processing unit, a display processing means for preparing a plurality of display data displayed on a display from the graphic or character data on the shared memory, and a display memory for storing the plurality of display data are connected to a bus. The display memory, the shared memory, and the external memory have first, second and third save areas for temporarily saving the overlapped display data when the plurality of display data are overlapped. The main memory is provided with a first control table for controlling display position, mutual priority for display, and a save area during overlap, regarding each of the plurality of display data stored in the display memory. The display processing means controls to display the plurality of display data on the display using the first table, the first, second and third save areas, and the display memory. In the first, second and third save areas, the first save area has highest priority and the third save area has lowest priority.

    摘要翻译： 中央处理单元，用于存储图形或字符数据的主存储器，外部存储器，用于输入图形或字符数据的输入装置，用于临时存储由中央处理单元读取的图形或字符数据的共享存储器，显示器 处理装置，用于从共享存储器上的图形或字符数据准备在显示器上显示的多个显示数据，以及用于存储多个显示数据的显示存储器连接到总线。 显示存储器，共享存储器和外部存储器具有用于在多个显示数据重叠时临时保存重叠显示数据的第一，第二和第三保存区域。 主存储器具有第一控制表，用于控制显示位置的显示位置，显示的相互优先级和重叠期间的保存区域，关于存储在显示存储器中的多个显示数据。 显示处理装置控制使用第一表，第一，第二和第三保存区以及显示存储器在显示器上显示多个显示数据。 在第一，第二和第三保存区域中，第一个保存区域具有最高优先级，第三个保存区域具有最低优先级。

    Memory circuit for graphic images
    14.
    发明授权
    Memory circuit for graphic images 失效
    内存电路图形图像

    公开(公告)号：US4868781A

    公开(公告)日：1989-09-19

    申请号：US240380

    申请日：1988-08-29

    申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kawabara

    发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kawabara

    IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393

    CPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

    摘要： A memory circuit including memory elements on which data read, write and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between external data and the data in the memory elements and the result of such operation is stored during a write cycle, thereby achieving a higher-speed operation.

    摘要翻译： 一种存储器电路，包括可任意执行数据读取，写入和存储操作的存储器元件，存储器元件具有二进制/算术运算功能。 在存储器周期内要执行的读取/修改/写入模式以及来自存储器元件和来自外部设备的数据的数据存在的间隔中，在外部数据和存储器元件中的数据之间执行操作，并且结果 在写入周期期间存储这种操作，从而实现更高速的操作。

    Automatic voltage regulation system for AC generator
    15.
    发明授权
    Automatic voltage regulation system for AC generator 失效
    交流发电机自动调压系统

    公开(公告)号：US4438385A

    公开(公告)日：1984-03-20

    申请号：US380263

    申请日：1982-05-20

    申请人： Hiroyasu Sato ,  Kazuaki Yamamoto ,  Hiroaki Aotsu

    发明人： Hiroyasu Sato ,  Kazuaki Yamamoto ,  Hiroaki Aotsu

    IPC分类号： G05B15/02 ,  H02P9/30 ,  H02P9/00 ,  H02P9/10

    CPC分类号： G05B15/02 ,  H02P9/305

    摘要： An output voltage of an AC generator is produced through a full-wave rectifier and converted into a digital signal by an A/D converter. This digital signal is compared with a reference signal, and in accordance with the difference therebetween, the firing angle of a thyristor is controlled to regulate the field current. Synchronous point detectors detect a synchronous point of the output voltage of the AC generator. A microprocessor computes a firing angle of the thyristor in accordance with the difference between the digital signal and the reference signal and produces a signal representing the computed firing angle upon detection of the synchronous point. The thyristor is fired at the firing angle computed by the microprocessor.

    摘要翻译： 交流发电机的输出电压通过全波整流器产生，并通过A / D转换器转换为数字信号。 该数字信号与参考信号进行比较，并且根据它们之间的差异，控制晶闸管的触发角度以调节励磁电流。 同步点检测器检测交流发电机的输出电压的同步点。 微处理器根据数字信号和参考信号之间的差异来计算晶闸管的触发角，并且在检测到同步点时产生表示计算的触发角的信号。 晶闸管以微处理器计算的触发角度点火。

    Method and apparatus for controlling excitation of a generator
    16.
    发明授权
    Method and apparatus for controlling excitation of a generator 失效
    用于控制发电机的激励的方法和装置

    公开(公告)号：US4326159A

    公开(公告)日：1982-04-20

    申请号：US71403

    申请日：1979-08-30

    申请人： Hiroaki Aotsu ,  Akira Isono ,  Tsutomu Inayama ,  Mamoru Fukushima

    发明人： Hiroaki Aotsu ,  Akira Isono ,  Tsutomu Inayama ,  Mamoru Fukushima

    IPC分类号： H02P9/10 ,  H02P9/14

    CPC分类号： H02P9/10

    摘要： Voltage, current and field voltage of a generator connected to an electric power system are sampled at a predetermined period for analog-digital conversion and then led to a digital computer. In addition to computation for AVR, the computer computes from its input the generator output power, and also monitors the occurrence of a fault, the removal of the fault and variation in the generator output in the system. After the occurrence of a fault, the field excitation of the generator is intensified until the generator output power reaches substantially a peak value, but after the peak value is substantially passed by, the excitation is conversely depressed to a value below the level which is present before the fault occurs. When the generator output power recovers the value which is present before the fault occurs, the computer returns to deliver the AVR output.

    摘要翻译： 连接到电力系统的发电机的电压，电流和电场电压以预定的时间被采样以进行模数转换，然后被引导到数字计算机。 除了计算AVR之外，计算机还可以从输入端计算发电机的输出功率，同时监测故障的发生，故障的消除和系统发电机输出的变化。 在故障发生之后，发电机的场激励增强，直到发电机输出功率达到基本上的峰值，但是在峰值基本上过去之后，激励被反而下降到低于存在的水平的值 在故障发生之前。 当发电机输出功率恢复故障发生之前存在的值时，计算机返回以传送AVR输出。

    Apparatus for bit operational process
    17.
    发明授权
    Apparatus for bit operational process 失效
    装置用于位操作过程

    公开(公告)号：US06437790B1

    公开(公告)日：2002-08-20

    申请号：US08487399

    申请日：1995-06-07

    申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Kiichiro Urabe

    发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Kiichiro Urabe

    IPC分类号： G09G102

    CPC分类号： G06F9/30018

    摘要： A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

    摘要翻译： 一种位操作处理器，具有第一地址操作单元，用于以字节或乘法字节为单位更新数据地址，以字节或多字节为单位进行操作;第二地址操作单元，用于以位为单位更新数据的地址 或多个位，响应于第二地址操作单元的地址提前结果而在第一地址操作单元上操作以提前地址的地址控制装置，以及用于获取由第一地址操作单元寻址的操作的字节宽数据的装置 地址操作单元，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。