公开(公告)号：US07282959B2

公开(公告)日：2007-10-16

申请号：US11072401

申请日：2005-03-07

申请人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

发明人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

IPC分类号： H03K19/094

CPC分类号： H01L27/1203 ,  G11C11/412 ,  H01L27/1108

摘要： It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

摘要翻译： 本发明的目的是提供使用四端双重绝缘栅场效应晶体管实现的CMOS电路，其中可以克服上述问题。 本发明的另一个目的是降低处于空闲状态或就绪状态的电路单元中的功耗，即减少静态功耗。 P型四端子双绝缘栅场效应晶体管的两个栅电极彼此电连接并且电连接到N型四端双绝缘栅的一个栅电极 场效应晶体管，由此形成CMOS电路的输入端子，并且通过控制N型四端子双绝缘栅极场效应晶体管的另一个栅极的电位来控制N型四端双重绝缘栅极场效应晶体管的阈值电压 型四端双绝缘栅场效应晶体管。

公开(公告)号：US20050199964A1

公开(公告)日：2005-09-15

申请号：US11072401

申请日：2005-03-07

申请人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

发明人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/76 ,  H03K19/0948

CPC分类号： H01L27/1203 ,  G11C11/412 ,  H01L27/1108

摘要： It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

摘要翻译： 本发明的目的是提供使用四端双重绝缘栅场效应晶体管实现的CMOS电路，其中可以克服上述问题。 本发明的另一个目的是降低处于空闲状态或就绪状态的电路单元中的功耗，即减少静态功耗。 P型四端子双绝缘栅场效应晶体管的两个栅电极彼此电连接并且电连接到N型四端双绝缘栅的一个栅电极 场效应晶体管，由此形成CMOS电路的输入端子，并且通过控制N型四端子双绝缘栅极场效应晶体管的另一个栅极的电位来控制N型四端双重绝缘栅极场效应晶体管的阈值电压 型四端双绝缘栅场效应晶体管。