公开(公告)号：US07049201B2

公开(公告)日：2006-05-23

申请号：US10703297

申请日：2003-11-06

申请人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

发明人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.

摘要翻译： 一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个， 基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极 结构和收集器区域。 基底结构和发射极结构优选地形成在相同的处理室中。

公开(公告)号：US5874764A

公开(公告)日：1999-02-23

申请号：US685792

申请日：1996-07-24

申请人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

发明人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

CPC分类号： H01L21/823475 ,  H01L21/823425 ,  H01L27/0203 ,  H01L27/088 ,  Y10S148/055

摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

摘要翻译： 高纵横比MOS器件的改进设计能够获得100％的产量。 该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。 高产量降低了制造成本。 引入模块化MOS概念，实现大通道宽度器件的100％产量。 模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。 这可以是具有适当尺寸以能够适应给定布局区域的多指装置。 因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。

公开(公告)号：US06372652B1

公开(公告)日：2002-04-16

申请号：US09494633

申请日：2000-01-31

申请人： Purakh Raj Verma ,  Zia Alan Shafi ,  Yu Shan ,  Zeng Zheng ,  Manju Sarkar ,  Shao-Fu Sanford Chu

发明人： Purakh Raj Verma ,  Zia Alan Shafi ,  Yu Shan ,  Zeng Zheng ,  Manju Sarkar ,  Shao-Fu Sanford Chu

IPC分类号： H01L21302

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element. The second dielectric layer and any overlying dielectric layers are patterned to form a fuse window opening, having a width greater than the sacrificial metal patch, using a first fuse window etch selective to the sacrificial metal patch. Then, the sacrificial metal patch is etched through the fuse window opening using a second fuse window etch selective to the fuse dielectric layer, leaving a reproducible thickness of the fuse dielectric layer overlying the fuse element; thereby providing a reproducible blowing wattage.

摘要翻译： 一种用于在熔丝电介质层和两个蚀刻工艺上使用牺牲金属贴片形成具有可再现的吹扫功率的薄膜电可熔电熔丝的方法; 其中所述第一蚀刻工艺对所述金属贴片是选择性的，并且所述第二蚀刻工艺对所述熔丝电介质层是选择性的。 在半导体结构上形成具有元件宽度的熔丝元件，并且在保险丝元件上形成熔丝电介质层。 在熔丝绝缘层上形成牺牲金属贴片; 其中所述贴片宽度大于所述熔丝元件宽度。 在牺牲金属贴片上形成第二电介质层，并且可以在第二电介质层上形成附加的金属层和电介质层，但是只有电介质层将保留在熔丝元件上方。 使用对牺牲金属贴片选择性的第一熔丝窗口蚀刻，将第二电介质层和任何上覆电介质层图案化以形成具有大于牺牲金属贴片的宽度的熔丝窗口。 然后，使用对熔丝电介质层选择性的第二熔丝窗蚀刻，通过熔丝窗口蚀刻牺牲金属贴片，留下覆于熔丝元件上的熔丝电介质层的可再现厚度; 从而提供可重复的吹制瓦数。

公开(公告)号：US06284590B1

公开(公告)日：2001-09-04

申请号：US09726655

申请日：2000-11-30

申请人： Randall Cher Liang Cha ,  Cheng Yeow Ng ,  Shao-Fu Sanford Chu ,  Tae Jong Lee ,  Chua Chee Tee

发明人： Randall Cher Liang Cha ,  Cheng Yeow Ng ,  Shao-Fu Sanford Chu ,  Tae Jong Lee ,  Chua Chee Tee

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L21/32139 ,  H01L28/60 ,  Y10S438/957

摘要： A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A first metal layer is deposited over the insulating layer. A capacitor dielectric layer is deposited overlying the first metal layer. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top metal electrode. A flowable material layer is deposited overlying the capacitor dielectric and the top metal electrode and anisotropically etched away to leave spacers on sidewalls of the top metal electrode. A photoresist mask is formed overlying the capacitor dielectric and the top metal electrode wherein the spacers provide extra photoresist thickness at the sidewalls of the top metal layer. The capacitor dielectric layer and the first metal layer are patterned wherein the patterned first metal layer forms a bottom metal electrode and wherein the spacers protect the top metal layer from etching during the patterning. The photoresist mask is removed, completing fabrication of a metal-insulator-metal capacitor.

摘要翻译： 描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。 绝缘层设置在半导体衬底上。 第一金属层沉积在绝缘层上。 沉积在第一金属层上的电容器电介质层。 将第二金属层沉积在电容器介电层上并被图案化以形成顶部金属电极。 将可流动材料层沉积在电容器电介质和顶部金属电极上，并各向异性地蚀刻掉，以在顶部金属电极的侧壁上留下间隔物。 形成覆盖电容器电介质和顶部金属电极的光致抗蚀剂掩模，其中间隔物在顶部金属层的侧壁处提供额外的光致抗蚀剂厚度。 电容器电介质层和第一金属层被图案化，其中图案化的第一金属层形成底部金属电极，并且其中间隔件在图案化期间保护顶部金属层不被蚀刻。 去除光致抗蚀剂掩模，完成金属 - 绝缘体 - 金属电容器的制造。

公开(公告)号：US5721144A

公开(公告)日：1998-02-24

申请号：US547180

申请日：1995-10-24

申请人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

发明人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088

CPC分类号： H01L21/823475 ,  H01L21/823425 ,  H01L27/0203 ,  H01L27/088 ,  Y10S148/055

摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

摘要翻译： 高纵横比MOS器件的改进设计能够获得100％的产量。 该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。 高产量降低了制造成本。 引入模块化MOS概念，实现大通道宽度器件的100％产量。 模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。 这可以是具有适当尺寸以能够适应给定布局区域的多指装置。 因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。