公开(公告)号：US07049201B2

公开(公告)日：2006-05-23

申请号：US10703297

申请日：2003-11-06

申请人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

发明人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.

摘要翻译： 一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个， 基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极 结构和收集器区域。 基底结构和发射极结构优选地形成在相同的处理室中。

公开(公告)号：US06372652B1

公开(公告)日：2002-04-16

申请号：US09494633

申请日：2000-01-31

申请人： Purakh Raj Verma ,  Zia Alan Shafi ,  Yu Shan ,  Zeng Zheng ,  Manju Sarkar ,  Shao-Fu Sanford Chu

发明人： Purakh Raj Verma ,  Zia Alan Shafi ,  Yu Shan ,  Zeng Zheng ,  Manju Sarkar ,  Shao-Fu Sanford Chu

IPC分类号： H01L21302

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element. The second dielectric layer and any overlying dielectric layers are patterned to form a fuse window opening, having a width greater than the sacrificial metal patch, using a first fuse window etch selective to the sacrificial metal patch. Then, the sacrificial metal patch is etched through the fuse window opening using a second fuse window etch selective to the fuse dielectric layer, leaving a reproducible thickness of the fuse dielectric layer overlying the fuse element; thereby providing a reproducible blowing wattage.

摘要翻译： 一种用于在熔丝电介质层和两个蚀刻工艺上使用牺牲金属贴片形成具有可再现的吹扫功率的薄膜电可熔电熔丝的方法; 其中所述第一蚀刻工艺对所述金属贴片是选择性的，并且所述第二蚀刻工艺对所述熔丝电介质层是选择性的。 在半导体结构上形成具有元件宽度的熔丝元件，并且在保险丝元件上形成熔丝电介质层。 在熔丝绝缘层上形成牺牲金属贴片; 其中所述贴片宽度大于所述熔丝元件宽度。 在牺牲金属贴片上形成第二电介质层，并且可以在第二电介质层上形成附加的金属层和电介质层，但是只有电介质层将保留在熔丝元件上方。 使用对牺牲金属贴片选择性的第一熔丝窗口蚀刻，将第二电介质层和任何上覆电介质层图案化以形成具有大于牺牲金属贴片的宽度的熔丝窗口。 然后，使用对熔丝电介质层选择性的第二熔丝窗蚀刻，通过熔丝窗口蚀刻牺牲金属贴片，留下覆于熔丝元件上的熔丝电介质层的可再现厚度; 从而提供可重复的吹制瓦数。

公开(公告)号：US06489191B2

公开(公告)日：2002-12-03

申请号：US10140571

申请日：2002-05-08

申请人： Kai Shao ,  Yimin Wang ,  Jian Xun Li ,  Shao-Fu Sanford Chu

发明人： Kai Shao ,  Yimin Wang ,  Jian Xun Li ,  Shao-Fu Sanford Chu

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  Y10S977/712

摘要： A method for forming a CMOS transistor gate with a self-aligned. channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshhold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.

摘要翻译： 一种用于形成具有自对准的CMOS晶体管栅极的方法。 通道植入。 提供具有第一有源区的半导体结构。 在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。 使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。 形成暴露第一通道植入物开口的第一通道植入物掩模。 通过第一通道植入物开口注入杂质离子以形成第一阈值调整区域和第一抗穿透区域。 在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。 去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

公开(公告)号：US06410394B1

公开(公告)日：2002-06-25

申请号：US09465305

申请日：1999-12-17

申请人： Kai Shao ,  Yimin Wang ,  Jian Xun Li ,  Shao-Fu Sanford Chu

发明人： Kai Shao ,  Yimin Wang ,  Jian Xun Li ,  Shao-Fu Sanford Chu

IPC分类号： H01L21336

CPC分类号： H01L21/823807 ,  Y10S977/712

摘要： A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.

摘要翻译： 一种用于形成具有自对准沟道植入物的CMOS晶体管栅极的方法。 提供具有第一有源区的半导体结构。 在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。 使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。 形成暴露第一通道植入物开口的第一通道植入物掩模。 杂质离子通过第一通道注入开口注入，以形成第一阈值调整区域和第一抗穿通区域。 在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。 去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

公开(公告)号：US6133079A

公开(公告)日：2000-10-17

申请号：US358985

申请日：1999-07-22

申请人： Min Zhu ,  Kai Shao ,  Shao-Fu Sanford Chu

发明人： Min Zhu ,  Kai Shao ,  Shao-Fu Sanford Chu

IPC分类号： H01L21/02 ,  H01L23/522 ,  H01L27/06 ,  H01L27/08 ,  H01L21/8238

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2924/0002

摘要： A method for reducing the capacitive coupling of an inductor on an integrated circuit chip is described. The method forms the inductor over an accumulation of dielectric layers used elsewhere in the integrated circuit. In addition two back-to-back reversed p/n junctions are formed within the silicon substrate below the inductor. The junctions are serially connected and, along with the capacitance of the dielectric layers, reduce the capacitive coupling of the inductor to the substrate by a factor of between about 2 and 20 over the that of the dielectric layers alone. The decrease in capacitance improves the performance of the inductor at high operating frequencies, for example, above1 GHz. The junctions are easily formed in a twin-well CMOS circuit by the addition of only a single additional processing step. The additional step comprises the deep implantation of phosphorous to form an n-type zone between the p-well and the substrate in the region over which the inductor is formed. The junctions are not externally biased and sustain continuous depletion regions between the inductor and the substrate.

摘要翻译： 描述了用于减小集成电路芯片上的电感器的电容耦合的方法。 该方法在集成电路中的其他地方使用的介电层的积累形成电感器。 此外，在电感器下面的硅衬底内形成两个背靠背的反向p / n结。 接头串联连接，并且与电介质层的电容一起，使电感器与衬底的电容耦合比单独的电介质层的耦合减小约2至20倍。 电容的减小改善了高工作频率下电感器的性能，例如高于1GHz。 通过添加仅一个附加的处理步骤，可以在双阱CMOS电路中容易地形成结。 附加步骤包括在形成电感器的区域中深度注入磷以在p阱和衬底之间形成n型区。 接点不是外部偏置的，并且在电感器和衬底之间维持连续的耗尽区。

公开(公告)号：US6124194A

公开(公告)日：2000-09-26

申请号：US439365

申请日：1999-11-15

申请人： Kai Shao ,  Yi Xu ,  Cerdin Lee ,  Shao-Fu Sanford Chu

发明人： Kai Shao ,  Yi Xu ,  Cerdin Lee ,  Shao-Fu Sanford Chu

IPC分类号： H01L21/768 ,  H01L23/525 ,  H07L29/00

CPC分类号： H01L21/7681 ,  H01L23/5252 ,  H01L2924/0002

摘要： A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via. Simultaneously, an anti-fuse metal line is formed over the fusing element to form an anti-fuse module within the anti-fuse area, and a dual damascene interconnect is formed over, and contacting with, the second metal line and within the interconnect area.

摘要翻译： 一种制造抗熔丝模块和双镶嵌互连结构的方法包括以下步骤。 提供具有被第一介电层覆盖的至少两个暴露的金属线的半导体结构。 第一金属线在反熔丝区内，第二金属线在互连区内。 第一金属通孔形成在反熔丝区域内的第一电介质层内，第一金属通孔接触第一金属线。 在第一介电层和第一金属通孔上沉积SiN层。 图案化SiN层以形成至少两个开口。 第一开口暴露第一金属通孔，第二开口暴露第二电介质层的第二金属线上方的一部分。 在图案化的SiN层状结构上沉积并图案化定影元件层，以在第一金属通孔之上形成定影元件。 同时，在熔断元件上方形成抗熔丝金属线，以在反熔丝区域内形成反熔丝模块，并且在第二金属线之间和互连区内形成双面镶嵌互连 。

公开(公告)号：US5874764A

公开(公告)日：1999-02-23

申请号：US685792

申请日：1996-07-24

申请人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

发明人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

CPC分类号： H01L21/823475 ,  H01L21/823425 ,  H01L27/0203 ,  H01L27/088 ,  Y10S148/055

摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

摘要翻译： 高纵横比MOS器件的改进设计能够获得100％的产量。 该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。 高产量降低了制造成本。 引入模块化MOS概念，实现大通道宽度器件的100％产量。 模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。 这可以是具有适当尺寸以能够适应给定布局区域的多指装置。 因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。

公开(公告)号：US06291307B1

公开(公告)日：2001-09-18

申请号：US09368863

申请日：1999-08-06

申请人： Shao-Fu Sanford Chu ,  Yang Pan ,  Wang Yimin ,  Kai Shao

发明人： Shao-Fu Sanford Chu ,  Yang Pan ,  Wang Yimin ,  Kai Shao

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/76224 ,  H01L27/0629

摘要： A new method is provided to create a capacitor over the surface of STI regions. The STI regions are first created in the surface of the substrate, a layer of sacrificial oxide is next blanket deposited over the substrate (thereby including the surface of the created STI regions). A depletion stop region overlying densely spaced STI regions is formed in the surface of the substrate by N+ ion implantation, N-well and P-well regions are formed surrounding the depletion stop region. An insulation layer is deposited. The sacrificial oxide and insulation layers are patterned and etched leaving the sacrificial oxide and the insulation layer in place where the capacitor is to be created. A layer of gate oxide is formed over the surface of the substrate, a layer of poly 2 is deposited for the bottom plate and the gate electrode. The conductivity of the gate electrode and the bottom plate of the capacitor is established by performing a selective N+ implant into the layer of poly 2 where the gate electrode and the bottom plate of the capacitor are to be formed. A layer of dielectric is deposited for the capacitor dielectric, a layer of in-situ doped poly 3 is deposited for the top plate of the capacitor. The layers of poly 3, dielectric and poly 2 are etched forming the capacitor structure and the gate electrode structure.

摘要翻译： 提供了一种新的方法来在STI区域的表面上形成电容器。 首先在衬底的表面中形成STI区，然后在衬底上沉积一层牺牲氧化物（从而包括所产生的STI区的表面）。 通过N +离子注入在衬底的表面中形成覆盖密集间隔的STI区的耗尽阻挡区，在耗尽阻挡区周围形成N阱和P阱区。 沉积绝缘层。 牺牲氧化物和绝缘层被图案化和蚀刻，留下牺牲氧化物和绝缘层到位于要产生电容器的位置。 在衬底的表面上形成栅极氧化层，为了沉积底层和栅电极，淀积一层聚二氧化硅。 通过对形成电容器的栅电极和底板的poly 2层进行选择性N +注入来建立电容器的栅电极和底板的导电性。 为电容器电介质沉积一层电介质，为电容器的顶板沉积一层原位掺杂的poly 3。 蚀刻形成电容器结构和栅极电极结构的聚3，电介质和聚合物2的层。

公开(公告)号：US06284594B1

公开(公告)日：2001-09-04

申请号：US09580607

申请日：2000-05-30

申请人： Yong Ju ,  Kai Shao ,  Yimin Wang ,  Shao-Fu Sanford Chu

发明人： Yong Ju ,  Kai Shao ,  Yimin Wang ,  Shao-Fu Sanford Chu

IPC分类号： H01L218242

CPC分类号： H01L27/0629 ,  H01L21/3144 ,  H01L28/40

摘要： A process for simultaneously forming a polysilicon gate structure, for a transfer gate transistor, and a polysilicon top plate, for a capacitor structure, on an underlying planar surface, has been developed. The process features the formation of a polysilicon bottom plate, for the capacitor structure, embedded in a first opening in composite insulator layer, and the formation of an active device region, for a transfer gate transistor structure, via the selective growth of an epitaxial silicon layer, in a second opening of the composite insulator layer, resulting in a planar top surface topography. The presence of this topography reduces the risk of residual polysilicon, present after patterning of the polysilicon gate structure, and of the capacitor, polysilicon top plate.

摘要翻译： 已经开发了用于在底层平面上形成用于电容器结构的传输栅极晶体管和多晶硅顶板的多晶硅栅极结构的工艺。 该方法的特征在于形成多晶硅底板，用于电容器结构，嵌入在复合绝缘体层中的第一开口中，并且通过外延硅的选择性生长形成用于传输栅晶体管结构的有源器件区 层，在复合绝缘体层的第二开口中，产生平坦的顶表面形貌。 这种形貌的存在降低了在多晶硅栅极结构图案化之后存在的残余多晶硅以及电容器，多晶硅顶板的风险。

公开(公告)号：US6159759A

公开(公告)日：2000-12-12

申请号：US443423

申请日：1999-11-19

申请人： Kai Shao ,  Cerdin Lee ,  Yi Xu ,  Shao-Fu Sanford Chu

发明人： Kai Shao ,  Cerdin Lee ,  Yi Xu ,  Shao-Fu Sanford Chu

IPC分类号： G02F1/1335 ,  G02F1/1362 ,  H01L21/00

CPC分类号： G02F1/133553 ,  G02F1/136277

摘要： A new method of forming liquid crystal displays has been achieved. Metal conductors are provided in an insulating layer overlying a semiconductor substrate. A first isolation layer is deposited. A first silicon nitride layer is deposited. The first silicon nitride layer is patterned to form openings for planned vias overlying the metal conductors. A second isolation layer is deposited. A second silicon nitride layer is deposited. The second silicon nitride layer is patterned to form masks overlying where dummy supports for the metal pixels are planned and to form openings to extend the planned vias. A third isolation layer is deposited. The third isolation layer is patterned to form openings for the planned metal pixels. The second isolation layer and the first isolation layer are etched through to complete the vias and the dummy supports. A metal layer is deposited filling the openings for the metal pixels, the dummy support, and the vias. The metal layer is polished down to the top surface of the third isolation layer to complete the metal pixels. A thin film passivation is deposited. A liquid crystal layer is deposited. A transparent image point electrode is formed to complete the liquid crystal display.

摘要翻译： 已经实现了一种形成液晶显示器的新方法。 金属导体设置在覆盖半​​导体衬底的绝缘层中。 沉积第一隔离层。 沉积第一氮化硅层。 图案化第一氮化硅层以形成覆盖金属导体的计划通孔的开口。 沉积第二隔离层。 沉积第二氮化硅层。 图案化第二氮化硅层以形成掩模，覆盖着金属像素的虚拟支撑被设计并形成扩展计划的通孔的开口。 沉积第三个隔离层。 图案化第三隔离层以形成用于计划的金属像素的开口。 蚀刻第二隔离层和第一隔离层以完成通孔和虚拟支撑。 沉积金属层，填充用于金属像素，虚拟支撑件和通孔的开口。 金属层被抛光到第三隔离层的顶表面以完成金属像素。 沉积薄膜钝化。 沉积液晶层。 形成透明图像点电极以完成液晶显示器。