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    Method of making trimmable modular MOSFETs for high aspect ratio applications
    1.
    发明授权
    Method of making trimmable modular MOSFETs for high aspect ratio applications 失效
    制造用于高宽高比应用的可调节模块化MOSFET的方法

    公开(公告)号：US5721144A

    公开(公告)日：1998-02-24

    申请号：US547180

    申请日：1995-10-24

    申请人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

    发明人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

    IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088

    CPC分类号： H01L21/823475 ,  H01L21/823425 ,  H01L27/0203 ,  H01L27/088 ,  Y10S148/055

    摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

    摘要翻译： 高纵横比MOS器件的改进设计能够获得100％的产量。 该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。 高产量降低了制造成本。 引入模块化MOS概念，实现大通道宽度器件的100％产量。 模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。 这可以是具有适当尺寸以能够适应给定布局区域的多指装置。 因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。

    Modular MOSFETS for high aspect ratio applications
    2.
    发明授权
    Modular MOSFETS for high aspect ratio applications 失效
    用于高宽高比应用的模块化MOSFET

    公开(公告)号：US5874764A

    公开(公告)日：1999-02-23

    申请号：US685792

    申请日：1996-07-24

    申请人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

    发明人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

    IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

    CPC分类号： H01L21/823475 ,  H01L21/823425 ,  H01L27/0203 ,  H01L27/088 ,  Y10S148/055

    摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

    摘要翻译： 高纵横比MOS器件的改进设计能够获得100％的产量。 该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。 高产量降低了制造成本。 引入模块化MOS概念，实现大通道宽度器件的100％产量。 模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。 这可以是具有适当尺寸以能够适应给定布局区域的多指装置。 因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。

    Discharge circuit in a semiconductor memory
    3.
    发明授权
    Discharge circuit in a semiconductor memory 失效
    半导体存储器中的放电电路

    公开(公告)号：US5736891A

    公开(公告)日：1998-04-07

    申请号：US585336

    申请日：1996-01-11

    申请人： Taqi Nasser Buti ,  Louis Lu-Chen Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary J. Saccamango ,  Hyun Jong Shin

    发明人： Taqi Nasser Buti ,  Louis Lu-Chen Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary J. Saccamango ,  Hyun Jong Shin

    IPC分类号： G11C16/30 ,  H03K17/10 ,  H03K17/687

    CPC分类号： H03K17/102 ,  G11C16/30 ,  H03K17/6872

    摘要： A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.

    摘要翻译： 用于半导体存储器的放电电路包括第一节点，用于接收具有第一和第二状态的控制信号的第二节点和连接在第一节点和地电位之间的电路以及连接到第二节点的电路。 当控制信号具有第一状态时，电路将第一节点耦合到地电位，并且当控制信号具有第二状态时，电路基本上将第一节点与地电势隔离。 电路包括用于限定第一节点和地电位之间的电流路径的第一子电路。 第一分支电路包括串联连接的多个晶体管，每个晶体管具有栅极，源极和漏极。 当控制信号具有第二状态时，电路还包括用于实现第一子电路的晶体管的预定栅极至源极和漏极至源极电压的第二子电路。

    Ramp-up rate control circuit for flash memory charge pump
    4.
    发明授权
    Ramp-up rate control circuit for flash memory charge pump 失效
    闪存充电泵的升压速率控制电路

    公开(公告)号：US5872733A

    公开(公告)日：1999-02-16

    申请号：US730628

    申请日：1996-10-21

    申请人： Taqi Nasser Buti ,  Louis Lu-Chen Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary Joseph Saccamango ,  Hyun Jong Shin

    发明人： Taqi Nasser Buti ,  Louis Lu-Chen Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary Joseph Saccamango ,  Hyun Jong Shin

    IPC分类号： G11C16/30 ,  H03K5/04 ,  H03F3/16 ,  H03L7/00

    CPC分类号： G11C16/30 ,  H03K5/04

    摘要： An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor. The flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. Other embodiments of the apparatus of the present invention are described herein.

    摘要翻译： 一种用于控制具有提供输出电压和输出电流的输出的电荷泵的上升速率的装置。 在一个实施例中，该装置包括具有输入，适于连接到地电势的输出和至少一个具有栅极，源极，漏极和主体的晶体管的电流泄放电路，并且限定源极和漏极之间的至少一个电流路径 形成输入和输出之间的当前路径。 主体适用于连接到电荷泵输出。 该装置还包括具有适于连接到电荷泵输出的输入端的控制电路和连接到泄放电路输入端的输出端。 控制电路为电流放电电路的输入提供电压电位，以控制电流放电电路晶体管的栅极 - 源极电压。 通过电流泄放路径的电流路径的电流流动是电荷泵输出的大小和泄放电路晶体管的栅极 - 源极电压的函数。 本文描述了本发明装置的其它实施例。

    High performance on-chip voltage regulator designs
    5.
    发明授权
    High performance on-chip voltage regulator designs 失效
    高性能片上稳压器设计

    公开(公告)号：US5721485A

    公开(公告)日：1998-02-24

    申请号：US582815

    申请日：1996-01-04

    申请人： Louis Lu-Chen Hsu ,  Toshiaki Kirihata ,  Somnuk Ratanaphanyarat ,  Hyun Jong Shin

    发明人： Louis Lu-Chen Hsu ,  Toshiaki Kirihata ,  Somnuk Ratanaphanyarat ,  Hyun Jong Shin

    IPC分类号： G06F1/26 ,  H03K3/01

    CPC分类号： G06F1/26 ,  Y10S323/901

    摘要： High performance on-chip voltage regulator designs are disclosed which have settling times which are fast enough to meet today's microprocessor/microcontroller requirements when they are entering an active mode from a passive mode. A first preferred embodiment provides a circuit in which a single pulse control signal is required to instantly raise Vy when the microprocessor is in the wake-up period. The circuit includes a charge pump, a differential amplifier, and a microprocessor connected to the power supply through a voltage regulating device. A second embodiment provides a circuit to stimulate Vint prior to CPU wake-up. The principle of operation of this embodiment is to stimulate the voltage regulating device prior to CPU wake-up. By stimulating (pulling down) the Vint node, the voltage regulating device will raise Vy and ready the microprocessor to draw a large current.

    摘要翻译： 公开了高性能片上稳压器设计，其具有足够快的建立时间，以在从被动模式进入活动模式时满足当今的微处理器/微控制器要求。 第一优选实施例提供了一种电路，其中当微处理器处于唤醒期间时，需要单脉冲控制信号来立即升高Vy。 电路包括电荷泵，差分放大器和通过电压调节装置连接到电源的微处理器。 第二实施例提供了在CPU唤醒之前刺激Vint的电路。 该实施例的操作原理是在CPU唤醒之前刺激电压调节装置。 通过刺激（下拉）Vint节点，电压调节装置将升高Vy并准备好微处理器绘制大电流。

    Method of discharging SOI floating body charge
    7.
    发明授权
    Method of discharging SOI floating body charge 失效
    放电SOI浮体电荷的方法

    公开(公告)号：US6151200A

    公开(公告)日：2000-11-21

    申请号：US452934

    申请日：1999-12-02

    申请人： Louis L. Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary J. Saccamango

    发明人： Louis L. Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary J. Saccamango

    IPC分类号： H02H9/04 ,  H02H9/00

    CPC分类号： H02H9/046

    摘要： Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.

    摘要翻译： 通过第一和第二放电电路对被监测的SOI器件的体放电的装置和方法。 当所监视的SOI器件的体电位处于使得所监视的SOI器件的体电量在正常工作周期时间容限内不能通过第一放电电路完全放电的水平时，选择性地激活第二放电电路。